Parasitic-Resistor Level Shift Circuit for dV/dt Latch Protection
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Solution Overview
Problem
Conventional level shift circuits in half-bridge circuits face challenges with increased delay times, current consumption, and circuit area due to the use of parasitic resistors, which are affected by temperature and voltage variations, leading to malfunctions and reduced responsiveness.
Innovation Solution
A level shift circuit configuration that includes series circuits with parasitic resistors and switching elements, an operation detection circuit, and a latch malfunction protection circuit, which adjusts resistance ratios and switching states to maintain impedance differences and prevent dV/dt noise-induced malfunctions, allowing for efficient operation without delay even with short set signal-reset signal pulse spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parasitic resistors are used in the level shift circuit, then the circuit can operate without wire bonding, but the delay time increases and responsiveness decreases
Solution Approach 1:
The patent changes the resistance values of parasitic resistors by adjusting their positions and dimensions in the semiconductor substrate. Specifically, it sets the resistance value of the first parasitic resistor to be different from the second parasitic resistor, creating an impedance difference that prevents malfunctions while maintaining fast response. This parameter optimization resolves the contradiction between eliminating wire bonding and reducing delay time.
Solution Approach 2:
The patent applies different resistance values to different parasitic resistors based on their specific positions and functions in the circuit. The first parasitic resistor (Rpar1) has a different resistance value than the second parasitic resistor (Rpar2), creating localized quality differences that optimize both manufacturability and performance without requiring wire bonding.
2Ease of manufacture
If parasitic resistors are used in the level shift circuit, then the circuit can be miniaturized, but the circuit area increases due to additional components
Solution Approach 1:
The patent merges the function of wire bonding with the semiconductor substrate's parasitic resistors. By utilizing the inherent parasitic resistors in the substrate and strategically positioning them, the circuit achieves wire-bonding-free operation without adding separate resistor components, thus minimizing circuit area while enabling miniaturization.
Solution Approach 2:
The patent employs the semiconductor substrate's own parasitic resistors to perform the level shifting function. The substrate's inherent resistive properties are harnessed to create the necessary impedance differences, eliminating the need for additional discrete components and reducing overall circuit area.
3Power
If parasitic resistors are used in the level shift circuit, then the circuit can operate at high voltage, but malfunctions occur due to dV/dt noise
Solution Approach 1:
The patent introduces asymmetry by setting different resistance values for the first and second parasitic resistors. This asymmetric configuration creates an impedance difference that prevents simultaneous low-level states of both level shift output signals, thereby preventing latch malfunctions caused by dV/dt noise during high-voltage operation.
Solution Approach 2:
The patent preemptively addresses the dV/dt noise issue by designing an asymmetric resistor configuration before malfunctions can occur. The different resistance values create inherent immunity against the simultaneous low-level condition that would trigger latch malfunctions, preventing the problem rather than reacting to it.
4Device complexity
If parasitic resistors are used in the level shift circuit, then the circuit can be simplified, but current consumption increases
Solution Approach 1:
The patent optimizes current consumption by carefully selecting and adjusting the resistance values of the parasitic resistors. By setting appropriate resistance values for Rpar1 and Rpar2, the circuit achieves simplified operation while controlling current flow to prevent excessive consumption, balancing simplicity with energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution ensures operation without delay and maintains durability against dV/dt noise, reducing current consumption and preventing malfunctions by optimizing impedance relationships and resistance values in the level shift circuit.
Implementation Method 1
a first series circuit in which a first parasitic resistor in a semiconductor substrate, a first switching element connected to an input terminal for receiving input of a first level shift input signal, and a first level shift output terminal for outputting a first level shift output signal are connected in series
Implementation Method 2
The level shift circuit uses parasitic resistors... configured of a latch malfunction protection circuit 121, a latch circuit 122, a first series circuit 124, a second series circuit 125, resistors R1 and R2
Implementation Method 3
a first switching element connected to an input terminal for receiving input of a first level shift input signal... a second switching element connected to an input terminal for receiving input of a second level shift input signal
Data Source
AI summary
A level shift circuit in which no adverse effect is produced on a delay time, regardless of the resistance values of resistors. The level shift circuit includes an operation detection circuit that outputs a nseten signal and a nresen signal in response to a state of output from first and second series circuits, a latch malfunction protection circuit connected to the operation detection circuit, a latch circuit connected through first to sixth resistors to first and second level shift output terminals of the first and second series circuits, first and second parasitic resistors, and third and fourth switching elements connected in parallel therewith, and fifth and sixth switching elements connected to a power source potential, a connection point of the first and second resistors or a connection point of the third and fourth resistors, and the operation detection circuit.