Parasitic Resistance Network Reduction for Full-Chip Current Density Simulation
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Solution Overview
Problem
Current rule-based ESD verification approaches are insufficient for modern IC designs, especially at 14 nm and below, due to increased complexity and sensitivity, requiring a more accurate and comprehensive analysis that full-circuit simulation can provide, but is hindered by high parasitic resistance data generation and memory usage challenges.
Innovation Solution
A method involving simulation to determine current data in parasitic resistance networks by injecting current, reducing non-current carrying parasitic resistors based on a threshold value, and performing full-circuit simulation using reduced networks to obtain current density information for circuit design verification, which includes ESD protection and electromigration checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-circuit simulation is performed using complete parasitic resistance networks, then measurement precision and reliability of ESD verification are improved, but memory usage and device complexity increase significantly
Solution Approach 1:
The patent segments the parasitic resistance network into multiple sub-networks based on current density thresholds. By dividing the network into regions of high and low current density, the simulation can focus computational resources on critical areas while simplifying non-critical areas, thereby reducing overall memory usage while maintaining measurement precision in ESD verification.
Solution Approach 2:
The patent applies partial action by selectively simulating only those parasitic resistance networks where current density exceeds a predetermined threshold. Instead of performing full-circuit simulation on all parasitic resistors, the method performs detailed simulation only on relevant sub-networks, reducing memory usage and device complexity while maintaining sufficient measurement precision for ESD verification.
2Measurement precision
If complete parasitic resistance networks are used in full-circuit simulation, then accuracy of current density analysis is improved, but memory usage becomes impractical for modern IC designs
Solution Approach 1:
The parasitic resistance network is segmented into multiple sub-networks based on current density levels. High current density sub-networks are simulated with full accuracy to maintain measurement precision, while low current density sub-networks are simplified or aggregated, significantly reducing the quantity of data stored in memory without compromising overall analysis accuracy.
Solution Approach 2:
The patent applies local quality by assigning different levels of simulation detail to different regions of the parasitic resistance network. Critical regions with high current density receive detailed simulation treatment to ensure accuracy, while non-critical regions use simplified models, optimizing the balance between measurement precision and memory usage.
3Productivity
If rule-based ESD verification is used, then productivity is improved, but measurement precision and reliability are insufficient for modern IC designs at 14 nm and below
Solution Approach 1:
The patent combines rule-based verification for rapid productivity with partial full-circuit simulation for critical regions. Rule-based methods provide quick initial verification to maintain productivity, while selective full-circuit simulation on high current density sub-networks provides the enhanced measurement precision needed for modern IC designs, achieving both efficiency and accuracy.
Data Source
AI summary
Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.