Automated NoC Design via Pareto Optimization for Latency and Power
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Solution Overview
Problem
As the number of cores in multi-core processors increases, network-on-chip (NoC) design faces challenges in efficiently scaling network topologies to manage data movement and communication between cores, leading to congestion and inefficiencies in power consumption and latency.
Innovation Solution
A Pareto-Optimization Framework (POF) is developed as an automated design tool that uses a Stochastic Optimization Framework (SOF) to explore various network configurations, employing optimization algorithms like Random Search, Special Greedy, and Simulated Annealing to determine optimal link allocations for low-latency and power-efficient NoC architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of cores in multi-core processors increases to achieve higher computational power, then computational performance is improved, but power consumption and network congestion increase
Solution Approach 1:
The patent applies parameter changes by optimizing network topology parameters (link allocations, routing paths, buffer sizes) to achieve better power efficiency. The automated design tool explores different parameter configurations to find optimal settings that reduce power consumption while maintaining computational performance in multi-core NoC systems.
2Power
If the number of cores in multi-core processors increases to achieve higher computational power, then computational performance is improved, but network congestion and latency increase
Solution Approach 1:
The patent optimizes network parameters including link allocations, routing protocols, and buffer configurations to reduce latency. The automated design tool evaluates multiple parameter combinations to identify configurations that minimize data transmission delays while supporting increased core counts for higher computational power.
3Device complexity
If traditional manual design methods are used for NoC architectures, then design complexity is manageable, but the ability to handle large-scale NoC designs is limited
Solution Approach 1:
The patent implements self-service through an automated design tool that independently performs network topology optimization without human intervention. The system automatically explores design spaces, evaluates configurations, and generates optimized NoC architectures, enabling handling of large-scale designs that would be impractical for manual design while maintaining manageable complexity through systematic exploration.
Solution Approach 2:
The patent replaces manual mechanical design processes with automated computational methods. The automated design tool uses algorithms and simulation to substitute human designers' manual analysis and optimization processes, enabling efficient exploration of large design spaces and generation of optimized NoC configurations at scale.
4Ease of manufacture
If existing network topologies are used, then implementation is straightforward, but scalability to large numbers of cores is limited
Solution Approach 1:
The patent applies segmentation by dividing the NoC design into modular components (routers, links, buffers) that can be independently optimized and reconfigured. This modular approach enables scalable designs by allowing the system to handle varying numbers of cores and configure appropriate network topologies automatically, maintaining implementation ease through standardized building blocks while achieving scalability.
Data Source
AI summary
Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.