Parity Bit Interleaving for RLL Error Propagation Control

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Solution Overview

Problem

High rate line codes in digital communications and storage technologies, such as disc drives, are vulnerable to forward error correction failure due to error propagation from line coding, which existing techniques like reverse coding attempt to address but result in inefficiencies and continued error propagation risks.

Innovation Solution

Implementing a zero overhead interleaver that interleaves parity symbols with data symbols using a systematic ECC code, ensuring deterministic interleaving patterns that maintain high rate RLL code efficiency while reducing error propagation by adjusting run-length constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high rate line codes are used to increase data transmission efficiency, then productivity is improved, but reliability deteriorates due to forward error correction failure from line coding error propagation

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidforward error correction reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an intermediary run-length constraint mechanism between the line coding process and forward error correction. By constraining the maximum number of consecutive identical bits (run-length) in the encoded data stream, the patent prevents error propagation that would otherwise occur during forward error correction processing, thus maintaining reliability while using high-rate line codes for improved productivity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If reverse coding technique is used to address error propagation, then reliability is improved, but device complexity increases and error propagation risk remains

Engineering Contradiction:
Improveerror propagation resistanceVSAvoidcoding technique complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter constraints of the line coding process by imposing run-length limitations (maximum consecutive identical bits) on the encoded output. This parameter change approach simplifies the overall system compared to reverse coding techniques, as it modifies the encoding constraints rather than requiring complex decoding and re-encoding operations, thereby reducing device complexity while maintaining reliability

Inventive Principle:
Principle #35Parameter changes

3Reliability

If run-length constraints are applied to reduce error propagation, then reliability is improved, but device complexity increases due to additional encoding requirements

Engineering Contradiction:
Improveerror propagation reductionVSAvoidencoding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies run-length constraints as a preliminary action during the line coding encoding process. By checking and enforcing the maximum run-length constraint at the point of encoding, the patent prevents error propagation conditions from occurring in the first place, rather than requiring complex post-processing or additional decoding stages, thus improving reliability while keeping the encoding process relatively simple

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8321750B2Interleaving parity bits into user bits to guarantee run-length constraint
Publication Date: 2012.11.27 LINK A MEDIA DEVICES CORP
  • US8321750B2 patent drawing
  • US8321750B2 patent drawing
  • US8321750B2 patent drawing

AI summary

RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.