Dual-Processor Parity Buffer Control for Faster Storage Writes
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Solution Overview
Problem
Existing storage devices experience time delays in generating and storing parity values, necessitating an efficient method to improve the parity operation process.
Innovation Solution
A storage device with a controller that includes a buffer memory and two processors: a first processor to manage state information of buffer areas and output control signals, and a second processor to generate and write parity values based on these signals, optimizing the parity operation by managing buffer area states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single processor is used to generate and store parity values, then the device complexity is reduced, but the time delay in parity operations increases
Solution Approach 1:
The controller is divided into two separate processors: a first processor dedicated to managing buffer area state information and generating control signals, and a second processor dedicated to generating and writing parity values. This segmentation allows parallel processing of different tasks, reducing the overall time delay in parity operations while maintaining manageable device complexity through functional separation.
Solution Approach 2:
The first processor preliminarily manages the state information of buffer areas and prepares control signals before the second processor generates and writes parity values. This preliminary preparation of buffer management and control signal generation enables the second processor to immediately write parity values without waiting for buffer status checks, thereby reducing time delay.
2Productivity
If buffer management is simplified, then the ease of operation is improved, but the productivity of parity operations decreases
Solution Approach 1:
The first processor automatically manages the state information of buffer areas and generates control signals based on this state information without requiring external intervention. This self-service approach to buffer management maintains high productivity by continuously monitoring and managing buffer states, while the automated nature of the process keeps the system easy to operate.
Solution Approach 2:
The first processor continuously monitors the state information of buffer areas and uses this feedback to generate appropriate control signals for the second processor. This feedback mechanism ensures that buffer management adapts to changing conditions, maintaining high parity operation productivity while the automated feedback loop simplifies operation by eliminating manual buffer management.
3Loss of time
If buffer areas are not allocated for parity operations, then the device complexity is reduced, but the time delay in storing parity values increases
Solution Approach 1:
The buffer memory is segmented into multiple buffer areas, with at least one specifically allocated for parity operations. This segmentation provides a dedicated storage space for parity values, enabling the second processor to write parity values immediately without waiting for main memory operations, thereby reducing time delay while maintaining organized and manageable buffer structure.
Solution Approach 2:
Buffer areas are preliminarily allocated and prepared for parity operations before the second processor generates parity values. This preliminary allocation of dedicated buffer space eliminates the need for runtime buffer management decisions, reducing time delay in storing parity values while keeping the buffer management system simple through pre-established allocation.
Data Source
AI summary
A first processor manages state information of a buffer area of a buffer memory used as a parity area in a parity operation mode and outputs a control signal according to the state information, and a second processor which performs a parity operation using the buffer area performs the parity operation according to the control signal of the first processor.