Parity Cache for Non-Volatile Memory Error Correction
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Solution Overview
Problem
Non-volatile memory (NVM) devices face challenges in error correction due to the inability to programmatically update parity cells without intervening erase operations in unidirectional devices and reliability issues in bidirectional devices, leading to errors and reliability problems.
Innovation Solution
Implementing a parity cache in volatile memory to extend error correction protection by enabling or disabling parity cells based on programming cycles and cache line management, allowing parity values to be stored in cache lines and flushed when necessary to maintain data integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity cells are programmed in unidirectional NVM devices, then data cells can be programmed, but parity cells cannot be updated without erase operations
Solution Approach 1:
The patent segments the parity storage function into two parts: parity cells in the NVM device for initial storage, and a parity cache in volatile memory for subsequent updates. This segmentation allows data cells to be programmed in the NVM while parity values can be updated in the volatile cache without requiring erase operations on the NVM parity cells.
Solution Approach 2:
The patent introduces a parity cache in volatile memory as an intermediary between the data cells and the parity cells. This intermediary allows parity values to be updated dynamically without directly programming the NVM parity cells, thus avoiding the limitation of unidirectional programming while maintaining error correction capability.
2Ease of operation
If parity cells are programmed bi-directionally in PGM devices, then parity values can be updated, but reliability problems occur in parity cells
Solution Approach 1:
The patent uses a volatile memory cache as an intermediary to perform all parity update operations. This eliminates the need to program parity cells bi-directionally in the NVM device, thus avoiding reliability problems while maintaining full parity update capability through the volatile cache.
Solution Approach 2:
The patent maintains a copy of parity values in the volatile memory cache. This copy can be updated freely without affecting the original parity cells in the NVM device, allowing flexible parity management while preserving the reliability of the NVM parity cells.
3Productivity
If parity cells are disabled in unidirectional NVM devices during second write operations, then programming can proceed, but error correction protection is lost
Solution Approach 1:
The patent introduces a parity cache in volatile memory as an intermediary that maintains error correction protection during write operations. When data cells are programmed, the parity cache is updated simultaneously without requiring parity cells to be disabled, thus maintaining both programming speed and error correction protection.
Solution Approach 2:
The patent performs preliminary action by pre-allocating a parity cache in volatile memory before write operations. This cache is prepared to receive parity values, allowing data programming to proceed without disabling parity protection, as the cache is already in place to handle parity updates.
Data Source
AI summary
Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.