Parity-Check Decoding via Encoder Reuse for Lower Circuit Complexity
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Solution Overview
Problem
The complexity of decoding procedures in error correcting codes increases with the size of the parity check matrix, making it challenging to efficiently decode data from rewritable non-volatile memory modules in portable devices.
Innovation Solution
A decoding method that reads a codeword from a rewritable non-volatile memory module, performs an encoding procedure on the message bits to generate second parity bits, and generates syndromes using both first and second parity bits to determine the validity of the codeword, allowing the encoding circuit to be reused and reducing the complexity of the decoding circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a larger parity check matrix is used to increase codeword length, then the error correction capability is improved, but the decoding circuit complexity increases
Solution Approach 1:
The encoding circuit is designed to perform multiple functions: it generates second parity bits from message bits during encoding, and also generates syndromes from first and second parity bits during decoding. This multi-functionality allows the same circuit hardware to be reused for both encoding and syndrome generation operations, reducing overall system complexity while maintaining error correction capability with larger codewords
2Productivity
If the parity check matrix size increases with codeword length, then more data can be stored and corrected, but the calculation complexity increases
Solution Approach 1:
The syndrome generation function is extracted from the traditional decoding circuit and implemented using the existing encoding circuit. By reusing the encoding circuit's logic to generate syndromes from parity bits, the patent eliminates the need for a separate complex decoding circuit, thereby reducing calculation complexity while maintaining the ability to process larger codewords with enhanced data processing capacity
Data Source
AI summary
A decoding method for a parity check code, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading a codeword belonging to the parity check code from a rewritable non-volatile memory module, wherein the codeword includes message bits and first parity bits; performing an encoding procedure of the parity check code on the message bits to generate second parity bits; and generating a plurality of syndromes corresponding to the codeword according to the first parity bits and the second parity bits, wherein the syndromes are used to determine whether the codeword is a valid codeword. Accordingly, a complexity of a decoding circuit is decreased.