Parity Check Matrix Layout for Multi-Error ECC Protection
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Solution Overview
Problem
Current error correction techniques for high-speed data links, such as those between a System on Chip (SoC) and RAM, face inefficiencies in error detection and correction, particularly with multiple errors, as they often require more bits than necessary for single error correction and double error detection (SECDED) protection, leading to miscorrections and undetected errors.
Innovation Solution
The implementation of a parity check matrix for error-correcting codes (ECC) that uses a greater number of bits than the minimum required for SECDED protection, specifically a 'weight 3 code' with 14-bit ECC, which optimizes row and column weights to enhance error detection and correction capabilities, including the calculation of new error syndromes and error location vectors to correct errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a minimum number of bits for SECDED protection is used, then the ECC size is reduced, but error detection and correction capabilities for multiple errors are insufficient
Solution Approach 1:
The patent increases the ECC bits from the minimum 9 bits to 14 bits, changing the parameter of code length to achieve weight-3 code properties. This parameter change enables the code to detect and correct multiple errors while maintaining optimal row and column weights in the parity check matrix, resolving the contradiction between ECC size and error handling capability.
2Reliability
If more bits are used for ECC beyond minimum SECDED requirements, then error detection and correction capabilities improve, but hardware complexity increases
Solution Approach 1:
The patent optimizes the local quality of the parity check matrix by ensuring that each row and column has a weight of exactly 3. This uniform local property throughout the matrix structure enables simplified hardware implementation with consistent logic gate requirements, reducing overall hardware complexity while maintaining enhanced error detection and correction capabilities.
3Device complexity
If optimized row and column weights are used in the parity check matrix, then error location logic is simplified, but the matrix construction becomes more complex
Solution Approach 1:
The patent applies preliminary action by pre-optimizing the parity check matrix construction algorithm to automatically generate matrices with uniform weight-3 rows and columns. This preliminary optimization of the construction process ensures that the resulting matrix has simplified error location logic, where the consistent weight structure enables straightforward syndrome decoding and error identification without complex conditional logic.
Data Source
AI summary
Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.