Parity Check Matrix for Triple Adjacent Error Detection
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Solution Overview
Problem
Existing memory systems face challenges in efficiently detecting and correcting triple adjacent errors, which can lead to data loss or corruption due to physical damage or errors in memory chips.
Innovation Solution
A memory device and system that implement a novel error correction technology using a parity check matrix configured with columns arranged in an odd-odd-even pattern and leading ones arranged in a stepped structure, enabling 1-bit error correction, 2-bit error detection, and 3-bit error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes are used, then single bit errors can be corrected, but triple adjacent errors cannot be detected
Solution Approach 1:
The patent changes the structural parameters of the parity check matrix by arranging columns in odd-odd-even degree order and organizing leading ones in a stepped structure. This parameter modification enables the matrix to detect triple adjacent errors while maintaining systematic encoding capabilities, thus improving error detection capability without proportionally increasing complexity
Solution Approach 2:
The parity check matrix is segmented into specific column groups with odd-odd-even degree patterns. This segmentation allows the matrix to systematically handle different error types (single bit, double bit, and triple adjacent errors) through distinct column configurations, enabling enhanced error detection while keeping the matrix structure organized and manageable
2Reliability
If the parity check matrix is configured for triple adjacent error detection, then error detection capability is improved, but decoding complexity increases
Solution Approach 1:
The patent introduces asymmetry in the parity check matrix through the odd-odd-even degree column arrangement and stepped leading one structure. This asymmetric configuration creates unique syndromes for triple adjacent errors that differ from conventional patterns, enabling detection while the structured asymmetry actually simplifies the decoding process by providing clear error identification patterns
Solution Approach 2:
The parity check matrix is pre-configured with odd-odd-even degree columns and stepped leading ones during the encoding phase. This preliminary arrangement ensures that when decoding occurs, the syndrome calculation automatically reveals error patterns without requiring complex real-time analysis, thus reducing decoding complexity despite enhanced detection capability
3Reliability
If additional error detection operations are added, then error detection capability is improved, but processing time increases
Solution Approach 1:
The parity check matrix is designed to perform multiple error detection functions simultaneously through its odd-odd-even degree column structure. A single syndrome calculation using this matrix can identify single bit errors, double bit errors, and triple adjacent errors in one unified operation, eliminating the need for separate detection processes and thus reducing processing time while maintaining multi-type error detection capability
Data Source
AI summary
A memory device according to various example embodiments includes a memory cell array having a plurality of memory cells connected to word lines and bit lines; and an error correction circuit configured to perform error correction on data read from the memory cell array, wherein the error correction circuit is configured to perform at least one of a 1-bit error correction operation, a 2-bit error detection operation, or a 3-bit error detection operation using a parity check matrix, and the parity check matrix is configured so that columns are arranged in an order of odd-odd-even degree, and leading one (LO) of each row is arranged in a stepped structure.