DRAM Parity Chip for Uncorrectable Error Recovery
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Solution Overview
Problem
Current DRAM technologies, such as DDR5, have unacceptably high uncorrectable error (UE) and silent data corruption (SDC) rates, which are insufficient for server systems requiring high data integrity standards, as they rely on single bit error correction and dual bit error detection, failing to correct dual bit errors and undetect silent data corruptions.
Innovation Solution
A system with additional DRAM chips for storing parity bits, where the memory controller performs exclusive OR operations to generate and store parity bits, allowing for data recovery from uncorrectable errors and identification of silent data corruptions by recreating data using parity bits from functional memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single bit error correction and dual bit error detection are used in DRAM chips, then the memory chips can detect and correct single bit errors, but dual bit errors remain uncorrectable and silent data corruptions go undetected
Solution Approach 1:
The memory system is segmented into multiple independent memory chips, each storing a portion of the total data. This segmentation allows the system to distribute data across multiple chips and use parity information from functional chips to recover from failures in failed chips, thereby improving overall data integrity without requiring each individual chip to have enhanced error correction capabilities.
Solution Approach 2:
A parity chip is introduced as an intermediary component that stores parity bits calculated from the data stored in multiple memory chips. This parity chip acts as a mediator that enables error detection and correction by providing redundant parity information that can be used to identify and recover from uncorrectable errors and silent data corruptions in the memory system.
2Reliability
If additional memory chips are added to store parity bits for error correction, then uncorrectable errors can be corrected and silent data corruptions can be detected, but the device complexity increases
Solution Approach 1:
The memory system is divided into functional memory chips that store data and a separate parity chip that stores parity bits. This segmentation allows the parity functionality to be isolated in a dedicated chip, simplifying the overall system architecture compared to integrating parity logic into each memory chip, while still achieving enhanced error correction and detection capabilities.
Solution Approach 2:
The parity chip serves multiple functions: it stores parity bits for error detection, provides redundancy for error correction, and enables the system to detect silent data corruptions. This multi-functionality consolidates multiple error handling operations into a single component, reducing overall device complexity while improving reliability.
Data Source
AI summary
The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.