Parity Error Detection Circuit for Post-Amble-Free Memory Strobes
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Solution Overview
Problem
High-speed memory devices face challenges in maintaining stable operation due to increased error probability, and existing parity error detection circuits fail to comply with communication protocols when data strobe signals lack a post-amble, leading to incorrect parity output signals.
Innovation Solution
Incorporating a parity error detection circuit that performs parity checks on data sampled by a data strobe signal without a post-amble, generating a parity error signal based on the burst length of the data, ensuring compliance with communication protocols by adjusting the output time period according to the burst length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the memory device is increased, then the data processing capacity is improved, but the probability of error generation increases
Solution Approach 1:
The patent implements a parity error detection circuit that performs feedback verification on data received through the data strobe signal. The circuit calculates parity bits and compares them with received parity information to detect errors, creating a closed-loop feedback mechanism that monitors and corrects transmission errors at high speeds without compromising reliability
2Device complexity
If a traditional parity error detection circuit is used with data strobe signals lacking post-amble, then the device complexity is reduced, but the compliance with communication protocols deteriorates
Solution Approach 1:
The patent employs dynamic timing control where the parity output signal is maintained until a specific time point determined by burst length parameters. This dynamic adjustment of signal duration allows the circuit to comply with various communication protocols (such as JEDEC standards) without requiring complex protocol-specific circuit designs, achieving adaptability through temporal flexibility rather than structural complexity
3Loss of time
If the parity output signal is reset immediately after parity check, then the response time is reduced, but the compliance with communication protocols requiring maintained output deteriorates
Solution Approach 1:
The patent pre-calculates and stores the time point at which the parity output signal should be maintained based on burst length parameters before actual data transmission occurs. This preliminary determination of signal duration allows the system to quickly process parity checks while ensuring the output signal persists for the correct duration required by communication protocols, eliminating the need for immediate reset
Data Source
AI summary
A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.