Clock-Synchronized Parity Check Circuit for XOR Delay Control

The patent introduces a clock signal to periodically synchronize the operation of XOR gates in the parity check circuit. The clock signal enables the XOR gates to operate in synchronized stages, converting the asynchronous delay problem into a periodic, controlled operation. This ensures that parity data is generated at predictable time intervals aligned with the clock cycle, eliminating timing accuracy deterioration while maintaining parity check capability.

The patent introduces a clock signal as an intermediary element that mediates between multiple XOR gates performing parity checks. The clock signal acts as a synchronization intermediary, coordinating the operation timing of all XOR gates and ensuring that their outputs are aligned. This intermediary mechanism resolves the asynchronous delay issue by providing a common timing reference for all parity check operations.

The patent uses periodic clock signals to control the operation timing of XOR gates. By aligning the parity check operations with the clock cycles, the timing setting becomes straightforward - operators only need to configure the clock frequency and phase, rather than manually adjusting complex multi-stage gate timing. This periodic control mechanism significantly improves timing setting accuracy while maintaining full parity check capability.

The patent implements timing feedback mechanisms where the clock signal provides continuous timing information back to the XOR gate operations. This feedback ensures that all parity check operations remain synchronized with the system clock, allowing for accurate and consistent timing settings. The feedback mechanism enables automatic timing adjustment and maintains timing accuracy without requiring complex manual configuration.

The patent designs the XOR gate circuit to serve multiple functions: during normal operation, it performs parity checks on incoming data; when an error is detected, the same circuit generates reconstruction signals by XORing the parity data with the erroneous data. This multi-functionality allows the circuit to provide both error detection and error correction capabilities without adding separate dedicated circuits, thereby improving data protection while minimizing circuit complexity increase.

The patent implements a mechanism where, upon detecting an error, the system discards the erroneous data and recovers the correct data by generating reconstruction signals from the stored parity data. The same hardware circuit that generated the parity data is reused to generate the reconstruction signals, rather than adding separate correction circuits. This approach provides robust data protection while keeping the circuit complexity manageable through resource reuse.