Alternating Parity Deskew Channel for SERDES Data Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The OIF SFI-5 SERDES framer interface is difficult to implement due to high logic gate requirements, leading to expensive and power-consuming solutions in high-speed ASIC technologies like SiGe and InP.
Innovation Solution
A method using a bit-oriented framing scheme with alternating odd-even parity bits to align data channels, reducing the number of logic gates and power consumption required for data line synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the OIF SFI-5 standard's byte-oriented framing scheme with A1/A2 bytes is used for deskew channel synchronization, then data channel alignment can be achieved, but the number of logic gates required increases significantly, leading to high power consumption and implementation cost
Solution Approach 1:
The patent changes the fundamental parameter of the framing scheme from byte-oriented (A1/A2 bytes) to bit-oriented (alternating parity bits). This parameter change reduces the complexity of synchronization logic while maintaining alignment reliability, directly resolving the contradiction between reliable alignment and low logic gate requirements
Solution Approach 2:
The patent extracts and eliminates the complex A1/A2 byte framing mechanism, retaining only the essential synchronization function through simpler alternating parity bits. This extraction removes unnecessary complexity while preserving the core alignment capability
2Reliability
If the OIF SFI-5 standard's deskew channel implementation is used, then data line skew can be compensated, but power consumption increases due to the large number of logic gates required
Solution Approach 1:
By changing from byte-oriented to bit-oriented framing, the patent significantly reduces the number of logic gates required for skew compensation, thereby directly reducing power consumption while maintaining the reliability of the deskew function
Solution Approach 2:
The patent replaces expensive, complex logic gate structures with simpler, more energy-efficient bit-oriented parity logic, achieving the same skew compensation function with lower power consumption
3Speed
If the OIF SFI-5 standard's framing approach is implemented in high-speed ASIC technologies (SiGe, InP), then data transmission at 2.5 Gbps can be achieved, but implementation cost increases due to high logic gate requirements
Solution Approach 1:
The bit-oriented framing approach with alternating parity bits reduces the logic gate count, making high-speed ASIC implementation more cost-effective while maintaining 2.5 Gbps transmission capability
Solution Approach 2:
By removing the complex A1/A2 byte framing mechanism and retaining only essential synchronization functions through simpler parity bits, the patent reduces implementation complexity and cost for high-speed ASIC technologies
Data Source
AI summary
The invention includes a method and apparatus for aligning a plurality of data channels using a deskew bitstream. The method includes receiving the deskew bitstream, identifying an aligned deskew frame by processing the deskew bitstream, identifying a data channel alignment position associated with each of the plurality of data channels by comparing a deskew channel comparison bit from the aligned deskew frame to a data channel comparison bit from each of the plurality of data channels, and selecting the plurality of data channel alignment positions associated with the respective plurality of data channels for aligning the plurality of data channels. The plurality of data channels are aligned in a manner for substantially reducing skew associated with the data channels. The deskew bitstream comprises a plurality of data bits associated with the data channels and a plurality of parity bits generated using at least a portion of the data bits.