Merging Parity and ECC Memory Blocks for Utilization
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Solution Overview
Problem
Existing memory systems face a tradeoff between error protection and memory utilization, as increased error protection requires more circuitry and memory space, which can reduce overall efficiency.
Innovation Solution
The solution involves merging parity-protected memory blocks with error correction code (ECC) protected blocks in a codeword, allowing for the repurposing of bits as metadata while maintaining error protection through the use of ECC symbols and parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more error protection data bits are used to increase error protection level, then data reliability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent merges parity-protected memory blocks with ECC-protected blocks in a single codeword structure. By combining these two previously separate protection mechanisms into one integrated codeword, the system achieves both parity error detection and ECC error correction capabilities while improving overall memory utilization through shared overhead bits.
Solution Approach 2:
The supplemental portion of the codeword is designed to serve multiple functions: it contains ECC symbols for error correction, parity bits for error detection, and can be repurposed as metadata when error protection requirements are reduced. This multi-functional design allows the same memory space to adapt to different protection levels and storage needs.
2Reliability
If error protection data bits are stored in memory circuits, then data integrity is improved, but circuit complexity increases
Solution Approach 1:
The patent combines parity protection circuits and ECC protection circuits into a unified error protection system. The memory control circuit processes both parity bits and ECC symbols through integrated logic, reducing the need for separate dedicated circuits for each protection mechanism and thereby lowering overall circuit complexity.
Solution Approach 2:
The error protection circuit is designed to perform multiple functions: generating parity bits, generating ECC symbols, detecting errors using parity, and correcting errors using ECC. This multi-functional circuit reduces the total number of specialized components needed while maintaining comprehensive data integrity protection.
3Quantity of substance
If supplemental portion bits are repurposed as metadata, then memory utilization is improved, but error protection capability deteriorates
Solution Approach 1:
The patent implements a dynamic error protection scheme where the function of the supplemental portion can change based on system requirements. When error protection needs are high, the supplemental portion contains full ECC symbols and parity bits. When protection requirements are reduced, these bits can be repurposed as metadata, allowing the system to adapt its protection level and utilization dynamically.
Solution Approach 2:
The system allows changing the protection parameter by adjusting how the supplemental portion is used. By modifying the configuration of error protection bits versus metadata bits in the supplemental portion, the system can transition between different protection levels and utilization modes without hardware changes.
Data Source
AI summary
A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.