Parity Engine for Configuration Register Data Integrity
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Solution Overview
Problem
Integrated circuit (IC) design houses often omit parity protection for configuration registers to reduce costs and complexity, which can lead to data integrity issues when configuration register values flip between write and read operations, especially in application-specific integrated circuit (ASIC) designs requiring parity protection.
Innovation Solution
Implementing a parity engine with a first-in, first-out (FIFO) for commands and a response FIFO for indications, which generates and stores parity data during write operations and provides it with read indications, ensuring data integrity by tracking commands and dequeuing them accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If parity protection is omitted for configuration registers to reduce cost and complexity, then device complexity and cost are reduced, but data integrity and reliability deteriorate due to potential latch value flips between write and read operations
Solution Approach 1:
The patent applies preliminary action by capturing and storing the parity value immediately after a write operation completes, before any potential latch flips can occur. The parity capture logic stores the parity of the written value in a dedicated register, ensuring that the correct parity is preserved and returned with subsequent read operations, even if the latch values change in the meantime.
Solution Approach 2:
The patent introduces an intermediary mechanism - a dedicated parity capture register and associated logic - that acts as a mediator between the write operation and the read operation. This intermediary stores the parity information separately from the configuration register latches, allowing the system to return the original parity value without relying on the current state of the latches.
2Productivity
If new parity is generated during read operations from current register values, then parity data is available for return, but data integrity deteriorates when latch flips occur between write and read operations causing incorrect parity to be returned
Solution Approach 1:
Instead of generating parity at read time, the system performs the parity calculation in advance during the write operation and stores the result. This preliminary calculation ensures that the parity value corresponds to the actual written data, not potentially corrupted current latch values, while still enabling fast read operations.
Solution Approach 2:
The patent creates a copy of the parity information in a dedicated register separate from the configuration register latches. This copy preserves the original parity value through subsequent latch flips, allowing the read operation to return accurate parity data without regenerating it from potentially changed latch values.
3Ease of manufacture
If configuration register IP is designed for FPGA without parity protection, then time-to-market and project cost are reduced, but adaptability to ASIC designs requiring parity protection deteriorates
Solution Approach 1:
The patent implements a universal solution that works for both FPGA and ASIC designs. By adding the parity capture logic that monitors write operations and stores parity values, the configuration register IP gains parity protection capability that can be utilized in ASIC designs requiring it, while maintaining compatibility with FPGA designs where it can be selectively enabled or disabled.
Solution Approach 2:
The patent enables the configuration register IP to change its behavior based on the target platform. The parity capture logic can be configured or enabled/disabled through parameters to provide parity protection when needed for ASIC designs while allowing simplified operation for FPGA designs, thus adapting to different application requirements.
Data Source
AI summary
Parity data associated with commands to, and indications from, a configuration register that includes a first command FIFO for receiving commands and a response FIFO for returning indications can be managed. Commands can be tracked by storing the commands in a second command FIFO and a command can be dequeued from the second command FIFO, in response to a command emerging from the response FIFO. Parity data can be generated from the data associated with a write operation, and stored in a parity latch corresponding to the configuration register, in response to the dequeued command being a successfully completed write operation. The generated parity data can be read from a parity latch corresponding to the configuration register and provided the generated parity data for return with an indication that the dequeued command is a successfully completed write operation.