Parity Error Alert Timing Interlock for Memory Devices

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Solution Overview

Problem

Existing memory devices face challenges in synchronizing parity error alerts with the completion of internal operations, leading to premature deactivation of parity error signals, which can result in collisions with ongoing commands and inefficiencies in memory operations.

Innovation Solution

The implementation of a parity error alert timing interlock system that aligns the timing of parity error alert signals with the completion of internal operations, ensuring that the alert signal is deactivated only after all pending operations are finished, thus preventing command collisions and optimizing memory device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the parity error alert signal is deactivated immediately after detection, then the signal pulse width is minimized, but the signal may be deactivated prematurely during ongoing internal operations causing command collisions

Engineering Contradiction:

Improveparity error alert pulse widthVSAvoidcommand execution safety

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The system performs preliminary detection of internal operation status before deactivating the parity error alert signal. The alert signal is held active until it is confirmed that all internal operations have completed, preventing premature deactivation while minimizing unnecessary extension of the alert pulse width.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the parity error alert signal is held active until all internal operations complete, then command execution safety is improved, but the alert pulse width exceeds minimum requirements and increases operational latency

Engineering Contradiction:

Improvecommand execution safetyVSAvoidoperational latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The alert signal duration is made dynamic rather than fixed. The signal is held active for the minimum required pulse width plus any additional time necessary to ensure internal operations complete, adapting to the actual system state rather than using a conservative fixed duration.

Inventive Principle:

Principle #15Dynamics

3Ease of manufacture

If a fixed minimum pulse width is used for the parity error alert signal, then manufacturing simplicity is maintained, but the signal may collide with ongoing commands when operations are still in progress

Engineering Contradiction:

Improvetiming circuit simplicityVSAvoidcommand execution safety

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The system uses feedback from internal operation status signals to control the deactivation timing of the parity error alert signal. The alert signal remains active as long as internal operations are detected to be in progress, providing feedback-based timing control that ensures safety while maintaining manufacturing feasibility.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11487610B2Methods for parity error alert timing interlock and memory devices and systems employing the same

Publication Date: 2022.11.01 LODESTAR LICENSING GROUP LLC

AI summary

Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.