Parity-Based Error Management for Associative Processing Memory
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Solution Overview
Problem
Memory systems, such as associative processing memory (APM) systems, face errors during storage and sensing operations, which impact performance, particularly when performing computations across multiple memory planes, and existing methods lack effective error management strategies.
Innovation Solution
The implementation of parity-based error management, where parity bits are carried through computational operations to detect and correct errors, by performing the same computation on operands and their corresponding parity bits, allowing for error detection and discretionary correction within the APM system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational operations are performed across multiple memory planes to improve processing throughput, then productivity is improved, but the likelihood of storage and sensing errors increases, worsening reliability
Solution Approach 1:
Parity bits are introduced as intermediary elements that accompany data through computational operations. These parity bits act as mediators that detect and correct errors without interfering with the primary computational function, allowing the system to maintain high throughput while improving reliability through error management
Solution Approach 2:
The patent creates redundant copies of data in the form of parity bits that are generated from and accompany the original data. These copied parity representations enable error detection and correction by comparing expected parity values with actual computed values, resolving the contradiction between processing speed and error rate
2Reliability
If parity-based error management is implemented to improve reliability, then error detection and correction capability is improved, but device complexity increases due to additional computational overhead
Solution Approach 1:
The patent merges error detection and correction functionality with the existing computational operation infrastructure. By carrying parity bits through the same computational planes used for data processing, the system combines reliability management with productivity-enhancing operations, reducing overall device complexity while improving error management capability
Data Source
AI summary
Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.