Parity Error Detection Verification in Circuit Simulation
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Solution Overview
Problem
The complexity of integrated circuit designs leads to significant time and resource consumption in simulations and tests, with existing methods often failing to detect design errors effectively, particularly in memory locations with lower read probabilities.
Innovation Solution
A method is introduced to simulate circuit designs by selecting memory locations with a higher probability of being read and inserting parity errors at these locations during simulation, ensuring error detection logic is properly verified and corresponding to real-world operation scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive simulations and tests are performed on complex integrated circuit designs, then design verification coverage is improved, but time and resource consumption increases significantly
Solution Approach 1:
The patent applies local quality by focusing error injection efforts on specific memory locations that have higher read probabilities rather than uniformly testing all memory locations. This selective approach concentrates verification resources on critical areas, improving detection effectiveness while reducing overall simulation time and computational resources required.
Solution Approach 2:
The patent uses partial action by injecting errors only in memory locations with high read probabilities rather than attempting to test all possible error scenarios. This partial approach achieves adequate verification coverage for critical paths without the excessive time and resource consumption of comprehensive exhaustive testing.
2Reliability
If error detection logic is verified using traditional simulation methods, then basic functionality is confirmed, but design errors in complex circuits are still overlooked
Solution Approach 1:
The patent changes the parameter of error injection strategy by using read probability as a selection criterion instead of random or uniform error distribution. This parameter change enables the verification system to adapt to the actual operational characteristics of the circuit, improving error detection capability in complex designs by focusing on statistically significant error scenarios.
Solution Approach 2:
The patent applies preliminary action by pre-calculating read probabilities for different memory locations before conducting the actual error detection simulation. This preliminary analysis allows the verification process to be strategically directed toward high-probability error locations, making the subsequent error detection more effective without requiring exhaustive testing of all circuit paths.
3Reliability
If memory locations with lower read probabilities are tested, then comprehensive coverage is achieved, but error detection efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating between high read probability and low read probability memory locations, applying error injection strategies selectively. High probability locations receive focused error injection and verification efforts, while low probability locations are tested with reduced intensity, optimizing the balance between coverage and efficiency based on local operational characteristics.
Solution Approach 2:
The patent changes the verification approach parameter from uniform error injection to probability-weighted error injection. By using read probability as a weighting parameter, the system achieves better error detection efficiency by concentrating testing resources on memory locations that are more likely to be accessed in actual operation, thereby improving the ratio of detection coverage to testing effort.
Data Source
AI summary
A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.