Parity Error Detection Circuit for Post-Amble-Free Memory Strobes
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Solution Overview
Problem
High-speed memory devices face challenges in maintaining stable operation due to increased error probability, and existing parity error detection circuits fail to comply with communication protocols when data strobe signals lack a post-amble, leading to incomplete parity check results.
Innovation Solution
Incorporating a parity error detection circuit that performs parity checks on data sampled by a data strobe signal without a post-amble, generating a parity error signal based on the burst length of the data, ensuring the parity output signal is maintained and output during a time period determined by the burst length, thus adhering to communication protocols like JEDEC standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a data strobe signal without a post-amble is used for high-speed data transmission, then transmission speed is improved, but parity check completeness deteriorates
Solution Approach 1:
The patent applies preliminary action by generating a mask signal in advance based on the burst length before the parity check is completed. This mask signal is then used to control the output timing of the parity check result, ensuring that the result is output for the correct duration even when the data strobe signal lacks a post-amble. The mask signal generation occurs during the data transmission phase, preparing the timing control mechanism before the parity verification is needed.
Solution Approach 2:
The mask signal acts as an intermediary between the data strobe signal and the parity check result output. Since the data strobe signal without post-amble cannot directly indicate when the parity check should be output, the mask signal serves as a mediator that translates the burst length information into appropriate output timing control, enabling the parity check result to be output for the correct duration.
2Adaptability or versatility
If parity check is performed on data sampled by data strobe signal without post-amble, then compliance with communication protocols is improved, but device complexity increases
Solution Approach 1:
The mask signal generator is designed to universally handle different burst lengths by receiving the burst length as input and generating appropriately timed mask signals. This multi-functional approach allows the same circuit to adapt to various data transmission scenarios without requiring separate dedicated circuits for each burst length, thereby achieving protocol compliance while limiting complexity growth.
Solution Approach 2:
The patent utilizes parameter changes by making the mask signal duration dependent on the burst length parameter. Instead of using a fixed timing mechanism, the system dynamically adjusts the mask signal duration based on the burst length input, allowing the parity check output to be properly timed for different data transmission scenarios while using a single adaptable circuit design.
Data Source
AI summary
A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.