Parity-Based Flip-Flop Memory for Low-Overhead Error Tolerance
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Solution Overview
Problem
Existing memory systems face challenges in efficiently detecting and correcting errors with high hardware and energy consumption, particularly when using parity bits or majority decision-makers, which are not desirable due to increased chip area and power consumption.
Innovation Solution
An error-tolerant memory circuit is designed with memory element pairs and parity generation circuits to calculate and compare parity bits, selectively outputting data from storage elements based on parity bit relationships to identify and correct errors with low hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are used to detect errors, then error detection capability is improved, but hardware consumption increases
Solution Approach 1:
The memory is divided into multiple memory element pairs, with each pair containing two memory storage elements that store the same data. This segmentation allows error detection through parity comparison within each pair without requiring extensive hardware across the entire memory system.
Solution Approach 2:
Each memory storage element has a copy stored in the paired memory element. The parity bit is generated by comparing these copies, allowing error detection through redundancy rather than requiring additional complex hardware circuits throughout the entire memory array.
2Reliability
If majority decision-makers are used to correct data, then error correction capability is improved, but chip area increases
Solution Approach 1:
The error correction function is extracted and simplified to a parity bit comparison mechanism that operates on memory element pairs. This eliminates the need for complex majority decision-making circuits while maintaining error correction capability through the parity check result.
Solution Approach 2:
The patent uses simple parity bits as a lightweight error detection and correction mechanism rather than implementing complex majority voters. The parity bit serves its purpose efficiently and can be implemented with minimal hardware resources, reducing overall chip area.
3Reliability
If majority decision-makers are used to correct data, then error correction capability is improved, but energy consumption increases
Solution Approach 1:
Instead of implementing full majority decision-making circuits that would require extensive logic gates and continuous operation, the patent uses partial action through parity bit comparison. The parity bit is generated and compared only when needed, reducing energy consumption while maintaining error correction capability.
Solution Approach 2:
The parity bit mechanism consumes significantly less energy than majority voters because it uses simpler logic circuits that operate only during read operations to compare parity bits, rather than continuous evaluation by complex decision-making circuits.
Data Source
AI summary
One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.