Parity Information Backup in Storage Controllers Against SRAM Volatility
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Solution Overview
Problem
Conventional data storage devices using flash memory face reliability issues due to program failures and silent read failures, leading to data loss and reduced performance, particularly when parity information is stored in volatile SRAM and requires frequent read operations from flash memory.
Innovation Solution
Implement a data storage device controller with a storage sub-system and security sub-system that uses a Bluetooth® interface to back up parity information in a secured cached database, ensuring user authentication and reducing reliance on volatile memory by transmitting parity information to an external device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity information is stored in volatile SRAM, then device size and power consumption are reduced, but data reliability deteriorates due to volatility and failure risks
Solution Approach 1:
The patent extracts the parity information storage function from the volatile SRAM and relocates it to non-volatile memory (NAND flash). This separation removes the reliability risks associated with volatility while maintaining the functional integrity of parity storage. The FTL layer is modified to write parity information to NAND flash instead of relying solely on SRAM, thereby eliminating data loss due to SRAM failures.
Solution Approach 2:
The patent implements a backup mechanism that stores parity information in both SRAM and NAND flash before failures occur. This dual-storage approach provides a cushion against potential SRAM failures, ensuring that parity information is preserved even if the primary SRAM storage fails. The system proactively maintains redundancy rather than reacting to failures after they occur.
2Reliability
If FTL transfers parity information to NAND, then data reliability is improved, but device performance deteriorates due to bottlenecks and time consumption
Solution Approach 1:
The patent implements preliminary action by having the FTL layer write parity information to NAND flash proactively during normal operations rather than waiting for failures or external requests. This background writing process ensures parity information is already stored in NAND before needed, eliminating the need for additional transfer operations when parity is required, thus maintaining high device performance while ensuring reliability.
Solution Approach 2:
The patent ensures continuity of useful action by making the FTL layer continuously manage and update parity information in NAND flash during normal data operations. This continuous background process eliminates gaps in parity storage, ensuring that parity information is always available and up-to-date without interrupting main data operations, thereby maintaining sustained high performance while ensuring reliability.
3Loss of information
If parity information is stored in SRAM, then device complexity is reduced, but loss of information increases due to volatility and corruption risks
Solution Approach 1:
The patent extracts the critical function of parity information storage from the unreliable SRAM memory and relocates it to non-volatile NAND flash memory. This extraction eliminates the risk of information loss due to SRAM volatility and corruption, while the FTL layer manages the transition and ensures data integrity without significantly increasing overall device complexity.
Solution Approach 2:
The patent creates a copy of the parity information storage function by duplicating the parity data in both SRAM and NAND flash. This copying approach ensures that even if SRAM fails or corrupts, the parity information is preserved in NAND flash, preventing information loss. The FTL layer manages both storage locations and coordinates reads from either source as needed.
Data Source
AI summary
Embodiments described herein provide a data storage device that backs-up parity information. The data storage device includes a memory and a data storage device controller coupled to the memory and including a storage sub-system and a security sub-system. The storage sub-system includes parity information within a second memory. The data storage device further includes a bus for transferring data between the data storage device controller and an external device in communication with the data storage device controller. The data storage device controller is configured to initiate a parity information back-up request, send, from the second memory of the storage sub-system, the parity information to the security sub-system based on the initiation of the parity information back-up request, and control the security sub-system to transmit the parity information to the external device.