Parity Interleaving in RLL Encoding to Prevent Catastrophic Sequences
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Solution Overview
Problem
Existing data encoding systems face inefficiencies due to the use of Low Rate RLL codes for error correction redundancy, which can lead to insufficient timing information and catastrophic sequences, degrading detector performance and increasing error propagation.
Innovation Solution
Implementing a system that encodes data using a High Rate RLL code and interleaves error correction parity with RLL-encoded data, avoiding the need for Low Rate RLL codes by spreading parity information throughout the data and using erasure decoding to determine parity symbols, thereby maintaining RLL constraints and improving system code rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Low Rate RLL code is used for RS ECC redundancy encoding, then RLL constraint is maintained in parity portion, but code rate is reduced and error propagation increases
Solution Approach 1:
The patent extracts the RLL encoding step from the parity portion by removing the Low Rate RLL encoder that was traditionally used. Instead, the system uses HR RLL encoding for the entire codeword (data + parity), and relies on interleaving to prevent catastrophic sequences, thereby eliminating the need for separate LR RLL encoding and improving code rate while maintaining reliability
Solution Approach 2:
The patent merges the encoding process by applying HR RLL encoding uniformly to both data and parity portions, rather than using different encoding rates for data and parity. This unification simplifies the encoding structure and improves overall code rate while the interleaver maintains the necessary constraints
2Reliability
If Low Rate RLL code is used for RS ECC redundancy, then timing information is sufficient, but device complexity increases due to additional encoding stages
Solution Approach 1:
The patent removes the separate Low Rate RLL encoding stage from the traditional two-stage encoding process. By using only HR RLL encoding followed by interleaving, the system reduces the number of encoding stages from two (HR RLL + LR RLL) to one (HR RLL + interleaving), simplifying the device while maintaining timing information through the interleaved structure
Solution Approach 2:
The HR RLL encoder is made universal by applying it to the entire codeword (both data and parity portions) rather than having separate encoders for different portions. The interleaver then serves the dual function of preventing catastrophic sequences and maintaining timing information, replacing the need for a second specialized encoder
3Reliability
If parity information is not interleaved with RLL-encoded data, then RLL constraint is fully maintained, but catastrophic sequences occur and detector performance degrades
Solution Approach 1:
The patent introduces an interleaver as an intermediary component between the HR RLL encoder and the storage/transmission medium. This interleaver rearranges the positions of data and parity symbols, preventing catastrophic sequences from occurring while maintaining the benefits of HR RLL encoding throughout the entire codeword
Data Source
AI summary
The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.