Parity-Guided Layered Error Correction for Lower-Power Memory Decoding
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Solution Overview
Problem
Existing methods for layered iterative error correction in memory devices do not effectively balance error correction performance with power consumption and latency, particularly in portable electronic devices, where stopping criteria are not optimized to conserve power without compromising data integrity.
Innovation Solution
Implementing a stopping criterion for layered iterative error correction based on parity checks, where the iterative error correction circuit stops once a particular layer's parity check is correct, transferring the codeword to an algebraic error correction circuit for further processing, thereby reducing unnecessary iterations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative error correction is performed with multiple layers and iterations to ensure data integrity, then error correction performance is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing error correction only on portions of the codeword that require it. The layered iterative error correction circuit processes different layers of the codeword separately, and the early termination circuit stops the correction process for layers that have already been successfully corrected, avoiding unnecessary processing of the entire codeword multiple times.
Solution Approach 2:
The patent implements dynamic adjustment of the error correction process through the early termination circuit. The circuit dynamically monitors the correction status of each layer and adjusts the number of iterations performed on subsequent layers based on previous correction results, allowing the system to adapt the correction intensity to the actual error conditions in the data.
2Reliability
If iterative error correction is performed with multiple layers and iterations to ensure data integrity, then error correction performance is improved, but latency increases
Solution Approach 1:
The patent applies partial action by performing error correction only on portions of the codeword that require it. The layered iterative error correction circuit processes different layers of the codeword separately, and the early termination circuit stops the correction process for layers that have already been successfully corrected, avoiding unnecessary processing of the entire codeword multiple times.
Solution Approach 2:
The patent implements dynamic adjustment of the error correction process through the early termination circuit. The circuit dynamically monitors the correction status of each layer and adjusts the number of iterations performed on subsequent layers based on previous correction results, allowing the system to adapt the correction intensity to the actual error conditions in the data.
3Reliability
If full iterative error correction is performed on all layers to ensure complete error correction, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing error correction only on portions of the codeword that require it. The layered iterative error correction circuit processes different layers of the codeword separately, and the early termination circuit stops the correction process for layers that have already been successfully corrected, avoiding unnecessary processing of the entire codeword multiple times.
Solution Approach 2:
The patent implements dynamic adjustment of the error correction process through the early termination circuit. The circuit dynamically monitors the correction status of each layer and adjusts the number of iterations performed on subsequent layers based on previous correction results, allowing the system to adapt the correction intensity to the actual error conditions in the data.
Data Source
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AI summary
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.