Parity Check Matrix Shortening for Double Error Correction
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Solution Overview
Problem
Existing error correction codes, such as single symbol error correction, are limited in correcting scattered errors and require additional redundancy bits, leading to increased hardware burden and power consumption.
Innovation Solution
A method and apparatus for generating error correction codes that enable single symbol and double error correction using a non-zero syndrome without adding redundancy bits, by extracting and generating a shortened parity check matrix with specific conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single symbol error correction is used to guarantee high reliability, then error correction capability is improved, but scattered errors cannot be corrected
Solution Approach 1:
The patent changes the parameters of the parity check matrix by extracting specific columns corresponding to the number of symbols in a codeword and setting two rightmost columns as a unit matrix. This parameter modification enables the system to achieve both single symbol error correction and double error correction using the same redundancy bits, thereby improving adaptability without sacrificing reliability.
2Reliability
If higher ratio of redundancy bits is used to guarantee higher reliability, then error correction capability is improved, but encoding/decoding time increases
Solution Approach 1:
The patent extracts only the necessary columns from the original parity check matrix that correspond to the number of symbols in a codeword. This extraction creates a shortened parity check matrix that maintains the essential error correction functionality while reducing the overall matrix size, thereby decreasing encoding/decoding time without compromising the ability to correct both single symbol and double errors.
Solution Approach 2:
The patent segments the parity check matrix by selecting specific columns and setting the two rightmost columns as a unit matrix. This segmentation creates a structured shortened parity check matrix that efficiently handles multiple error types. By dividing the problem into manageable matrix components, the system achieves comprehensive error correction with reduced computational overhead.
3Reliability
If higher ratio of redundancy bits is used to guarantee higher reliability, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential columns from the parity check matrix, creating a shortened version that maintains error correction capability while reducing the computational workload. This extraction reduces the number of operations required for encoding and decoding, thereby lowering power consumption without sacrificing the ability to correct single symbol and double errors.
Solution Approach 2:
By segmenting the parity check matrix into specific column selections and setting the two rightmost columns as a unit matrix, the patent creates an efficient structure that minimizes computational complexity. This segmented approach reduces the power required for encoding/decoding operations while preserving comprehensive error correction functionality.
4Reliability
If higher ratio of redundancy bits is used to guarantee higher reliability, then error correction capability is improved, but area burden increases
Solution Approach 1:
The patent extracts only the necessary columns from the original parity check matrix, creating a shortened matrix that maintains the essential error correction functionality. This extraction reduces the hardware resources required to implement the error correction code, thereby decreasing area burden while preserving the capability to correct both single symbol and double errors.
Solution Approach 2:
The patent segments the parity check matrix by selecting specific columns and configuring the two rightmost columns as a unit matrix. This segmentation creates a compact structure that can be implemented with fewer hardware resources, reducing area burden while maintaining comprehensive error correction capability for both single symbol and double errors.
5Reliability
If additional redundancy bits are added to enable double error correction, then error correction capability is improved, but hardware burden increases
Solution Approach 1:
The patent changes the parameters of the parity check matrix by extracting specific columns and setting the two rightmost columns as a unit matrix. This parameter modification enables the system to achieve double error correction capability without adding extra redundancy bits. The shortened parity check matrix maintains the same bit length while expanding error correction capability, thereby avoiding increased hardware burden.
Data Source
AI summary
There is provided a code generation method. The method comprises extracting columns corresponding to the number of symbols of a codeword from a parity check matrix of an error correction code; generating a shortened parity check matrix for the error correction code on the basis of the columns corresponding to the number of symbols of the codeword; checking whether the shortened parity check matrix includes an independent nonzero syndrome for each of a single symbol error and a double error; and generating a parity check matrix for a correction of the single symbol error corresponding to the number of bits of the shortened parity check matrix and a correction of the double error corresponding to the number of bits of the shortened parity check matrix if the shortened parity check matrix includes the independent nonzero syndrome for each of the single symbol error and the double error.