Parity Check Matrix ECC for Flash Memory Space Constraints
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Solution Overview
Problem
Existing memory devices face challenges in efficiently managing data access and error correction in MLC flash memories, leading to increased storage space requirements and costs due to the need for pre-calculated information for ECC processing.
Innovation Solution
A data accessing method using a parity check matrix with partial sequential information, where the memory controller generates a parity check matrix with specific structures to perform syndrome calculation, error detection, and error correction, reducing the need for large storage spaces and look-up tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-calculated information is used for ECC processing to prevent encoding/decoding delay, then encoding/decoding speed is improved, but internal storage space requirements increase significantly
Solution Approach 1:
The parity check matrix is segmented into multiple sub-matrices, where only portions requiring pre-calculation are pre-computed and stored. This segmentation allows the system to maintain high decoding speed for critical operations while avoiding the need to pre-store entire large matrices, thus reducing internal storage requirements.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing only the essential portions of the parity check matrix that are needed for syndrome calculation and error correction. This selective pre-computation enables fast decoding without requiring excessive storage space for complete matrix pre-processing.
2Adaptability or versatility
If the controller IC supports various ECC processing specifications to meet different memory device manufacturer requirements, then adaptability is improved, but internal storage space must be forcibly increased causing cost increases
Solution Approach 1:
The patent implements a universal parity check matrix structure that can accommodate multiple ECC specifications and memory device types. By designing a flexible matrix framework with configurable sub-matrices, the controller IC can support various manufacturers' requirements without needing separate large storage areas for each specification, thus maintaining adaptability while controlling storage space requirements.
Solution Approach 2:
The patent enables parameter changes in the parity check matrix configuration to adapt to different ECC specifications. By dynamically adjusting matrix dimensions, sub-matrix arrangements, and pre-computation levels based on the specific memory device type and ECC requirements, the system achieves multi-specification support without proportionally increasing internal storage space.
Data Source
AI summary
A data accessing method using data protection with aid of a parity check matrix having partial sequential information, and associated apparatus such as memory device, memory controller, and decoding circuit thereof are provided. The data accessing method may include: in response to a read request, starting receiving protected data corresponding to the read request from predetermined storage space; generating the parity check matrix; performing syndrome calculation based on the parity check matrix according to a codeword to generate and output a syndrome for the codeword; performing error detection according to the syndrome to generate and output a decoding result signal, and performing error location decoding according to the syndrome to generate and output an error location; performing error correction of the codeword, to correct an error at the error location of the codeword; and performing further processing according to the one or more codewords obtained from the protected data.