Parity Check Matrix Optimization for Multi-Error ECC Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current error-correcting code (ECC) techniques for high-speed data links, such as those between a System on Chip (SoC) and RAM, face limitations in efficiently detecting and correcting multiple errors, particularly in scenarios where the number of errors exceeds the minimum required for single error correction and double error detection (SECDED) protection.
Innovation Solution
The implementation of a parity check matrix representing an ECC that uses more than the minimum number of bits required for SECDED protection, specifically a 'weight 3 code' with 14-bit ECC, which optimizes the sum of squared row weights and enhances error detection capabilities by calculating new error syndromes and storing them in a set, thereby improving the detection of multiple errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If minimum ECC bits for SECDED protection are used, then hardware complexity is reduced, but error detection capability for multiple errors is insufficient
Solution Approach 1:
The patent changes the parameter of ECC code length from the minimum required for SECDED to an optimized length that provides enhanced multiple error detection capability. Specifically, it uses a (63, 57) extended Hamming code instead of the minimum (63, 56) SECDED code, adding one extra parity bit to improve error detection while maintaining reasonable hardware complexity.
Solution Approach 2:
The patent pre-calculates and stores syndrome values for all possible single-bit and double-bit error patterns in a lookup table during system initialization. This preliminary action enables the decoder to quickly detect multiple errors by comparing actual syndromes against pre-computed values, improving detection capability without requiring complex real-time computation hardware.
2Reliability
If more ECC bits are used beyond minimum SECDED requirements, then multiple error detection is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the error detection process into distinct stages: syndrome calculation, lookup table comparison for single-bit errors, and pattern matching for double-bit errors. This segmentation allows each component to be optimized independently, improving multiple error detection capability while controlling overall hardware complexity through modular design.
Solution Approach 2:
The patent uses a lookup table that stores pre-computed syndrome patterns as copies of expected error signatures. By copying and storing these patterns in memory, the system can efficiently compare actual syndromes against multiple possible error patterns simultaneously, enhancing detection capability without requiring complex real-time computation hardware for each comparison.
3Measurement precision
If optimized parity check matrix is used, then error correction accuracy is improved, but computation time increases
Solution Approach 1:
The patent pre-calculates all possible syndrome values and their corresponding error patterns during system initialization and stores them in lookup tables. This preliminary action transforms the error correction process from complex real-time computation to simple table lookup operations, significantly reducing computation time while maintaining high error correction accuracy through the use of an optimized parity check matrix.
Solution Approach 2:
The patent replaces complex mechanical computation operations with electronic lookup table access. Instead of performing real-time matrix multiplication and syndrome calculation for each error pattern, the system substitutes these mechanical computations with rapid memory access and comparison operations, reducing computation time while maintaining accuracy through the optimized parity check matrix structure.
Data Source
AI summary
Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.