Multi-Page Parity Metadata for SSD Power Loss Recovery

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Solution Overview

Problem

Traditional SSDs face data loss risks due to unexpected power losses, which current error correction and redundancy methods struggle to fully mitigate, especially in scenarios involving back-to-back power loss events, leading to increased firmware complexity and memory usage.

Innovation Solution

Implementing a memory system with multiple parity groups and metadata flags to identify and manage asynchronous power loss-impacted pages, allowing for efficient exclusion of affected pages during data reconstruction and reducing the need for extensive bit maps and additional RAM space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional SSDs use standard error correction and redundancy schemes to protect against power loss, then data reliability improves, but device complexity and firmware complexity increase

Engineering Contradiction:
Improvedata protectionVSAvoiderror correction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the metadata structure by introducing specific flags (e.g., APL flag, host power loss flag) that divide the error handling into distinct categories. This segmentation allows the firmware to quickly identify and handle different types of power loss events without analyzing the entire metadata structure, thereby reducing firmware complexity while maintaining data protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-setting flags in the metadata during normal operation to indicate potential power loss scenarios. When an actual power loss occurs, the system can immediately detect these pre-set flags and execute appropriate recovery procedures without needing to perform complex analysis, thus reducing both device and firmware complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional SSDs implement comprehensive redundancy schemes to handle asynchronous power loss, then data reliability improves, but RAM usage increases

Engineering Contradiction:
Improvedata protectionVSAvoidRAM usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the power loss detection and handling logic from the main firmware execution flow and embeds it directly into the metadata structure through flags. By taking out the complex decision-making logic from RAM-based firmware and encoding it in the metadata itself, the system reduces RAM usage while maintaining comprehensive power loss protection capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses copying by storing power loss status information in the metadata (which persists across power cycles) rather than maintaining large buffers in RAM. The flags in the metadata serve as copies of the power loss state, allowing the system to recover without needing to maintain extensive redundant data in volatile memory.

Inventive Principle:
Principle #26Copying

3Device complexity

If traditional SSDs use simple metadata structures without power loss flags, then device complexity decreases, but data loss occurs during asynchronous power loss

Engineering Contradiction:
Improvemetadata structure complexityVSAvoiddata loss
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The patent applies preliminary anti-action by preemptively setting flags in the metadata to indicate potential power loss conditions before they actually cause data corruption. This preliminary marking allows the recovery process to identify and protect affected data, preventing information loss while adding only minimal complexity to the metadata structure.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent introduces flags as intermediary elements between the power loss event and the data. These flags act as mediators that carry information about power loss conditions without requiring complex metadata structures. The flags serve as a simple intermediate layer that enables reliable data protection with minimal added complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10747612B2Multi-page parity protection with power loss handling
Publication Date: 2020.08.18 MICRON TECHNOLOGY INC
  • US10747612B2 patent drawing
  • US10747612B2 patent drawing
  • US10747612B2 patent drawing

AI summary

A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.