Parity Offload for NVMe Storage Devices
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Solution Overview
Problem
Current non-volatile memory systems face performance bottlenecks due to the need for parity computations being performed on hosts or intermediate CPU systems, which slows down high-performance writes in storage systems like solid state drives.
Innovation Solution
Offloading parity computations to non-volatile memory-based data storage systems, such as flash memory-based solid state drives, by identifying a Redundancy Coding stripe and designating a specific data storage device to compute and store parity information, thereby shifting the computational burden from hosts or CPUs to the storage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity computations are performed on hosts or intermediate CPU systems, then data integrity can be ensured, but system throughput and write performance deteriorate due to computational bottlenecks
Solution Approach 1:
The patent extracts the parity computation function from the host CPU system and relocates it to the storage device's embedded controller. This separation removes the computational bottleneck from the host system, allowing write operations to proceed at full speed while the storage device independently computes and stores parity information for data integrity.
Solution Approach 2:
The storage device is empowered to perform its own parity computations internally without requiring host CPU intervention. The embedded controller within the storage device self-manages the parity calculation and storage operations, making the system self-sufficient for error correction while maintaining high write throughput.
2Productivity
If parity computations are offloaded to storage devices, then write throughput is improved, but device complexity increases due to additional computational requirements
Solution Approach 1:
The storage device's embedded controller is designed to perform multiple functions: data reception, parity computation, parity storage, and data integrity verification. By making the controller multi-functional, the patent avoids adding separate dedicated hardware for each function, thereby limiting the increase in overall device complexity while achieving high write throughput.
3Reliability
If multiple data storage devices are used in a Redundancy Coding stripe, then data reliability is enhanced, but the time required for parity computation and storage increases
Solution Approach 1:
The patent implements preliminary action by having the storage device receive and buffer incoming data before parity computation is required. The embedded controller prepares the data in advance and performs parity calculations on buffered data rather than in real-time during the write operation, significantly reducing the time penalty associated with multi-device redundancy.
Data Source
AI summary
A system and method improve the performance of non-volatile memory storage by offloading parity computations to facilitate high speed data transfers, including direct memory access (DMA) transfers, between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., SSD). In conjunction with writing to non-volatile memory storage, a stripe map is used to target a selected data storage device for parity generation. All data of a stripe is transmitted to the selected data storage device to generate the parity and the generated parity is propagated from the selected data storage device to other data storage devices in the stripe. The data for the stripe may also be propagated from the selected data storage device to the other data storage devices in the stripe.