Memory Controller Parity Pipeline for Faster Reliable Data Writes

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Solution Overview

Problem

Current data path protection technologies in memory systems face challenges in increasing data reliability while reducing operation time during write operations in non-volatile memory devices.

Innovation Solution

A controller is implemented with Error Correction Code (ECC) encoding, Low Density Parity Check (LDPC) encoding, and syndrome check operations to enhance data reliability by adding and correcting parities during data transfer between a host and a non-volatile memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple encoding operations (ECC, LDPC) and error check operations are performed during data transfer, then data reliability is improved, but operation time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing ECC encoding and adding parities to data before it is stored in the buffer. This preliminary processing allows the buffer to store pre-processed data that requires fewer operations during retrieval, thereby reducing the total operation time while maintaining data reliability through pre-applied error correction codes and parity bits

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple buffers are used to store data during encoding operations, then data processing capability is improved, but device complexity increases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidnumber of buffers
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single buffer that performs multiple functions: storing original data during write operations, storing encoded data during read operations, and supporting both write and read operations sequentially. This multi-functional buffer design eliminates the need for separate buffers for different operations, reducing device complexity while maintaining high data processing capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11099932B2Controller and memory system
Publication Date: 2021.08.24 SK HYNIX INC
  • US11099932B2 patent drawing
  • US11099932B2 patent drawing
  • US11099932B2 patent drawing

AI summary

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.