Parity-Protected RAM for Uninterrupted Aircraft Control Software
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Solution Overview
Problem
Avionic control systems face interruptions and time delays due to single event upsets (SEUs) caused by ion or electromagnetic radiation, which alter data in RAM, leading to incorrect byte values and system faults.
Innovation Solution
An aircraft control system with a parity-protected random access memory (PPRAM) that generates and checks parity bits for static data copies, allowing seamless switching to a new copy upon detection of a parity fault, ensuring uninterrupted execution of control software by reconfiguring the memory management unit (MMU) to access a different data copy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control system uses traditional RAM without parity protection, then the system operation is simple and fast, but the system reliability deteriorates due to SEU-induced data corruption
Solution Approach 1:
The memory system is segmented into multiple independent static data copies (at least two copies) stored in RAM. Each copy is protected by its own parity bits, allowing the system to divide the data storage function across multiple segments to maintain reliability while managing complexity through modular organization.
Solution Approach 2:
The patent implements redundancy by creating and storing multiple copies of static data in RAM. When data is written, at least two identical copies are stored with associated parity bits. This copying approach enables fault detection and correction without requiring complex error-correcting code algorithms, balancing reliability improvement with acceptable system complexity.
2Reliability
If the control system implements parity protection with multiple static data copies, then the system can detect and correct SEU faults, but the memory usage and system complexity increase
Solution Approach 1:
The system performs preliminary actions by pre-storing multiple static data copies and their associated parity bits in RAM before operation. This preliminary preparation allows the MMU to quickly switch to backup copies when faults are detected, avoiding the need for complex real-time error correction algorithms and reducing the computational overhead during critical operations.
Solution Approach 2:
The parity bits serve as intermediaries between the stored data and the fault detection mechanism. Rather than requiring complex comparison logic between multiple data copies, the parity bits provide a simple intermediary check that可以快速 identify data corruption, reducing the complexity of the fault detection process while maintaining high reliability.
3Reliability
If a fault is detected in the control system, then the system can identify errors, but traditional resetting causes time delays and interrupts execution
Solution Approach 1:
The system maintains continuity of useful action by implementing seamless switching between static data copies through the MMU. When a fault is detected via parity check, the system continuously operates by switching to a backup copy without interruption or reset. This eliminates the time loss associated with traditional system resetting while maintaining fault identification capability, ensuring uninterrupted control software execution.
Solution Approach 2:
The system implements feedback through the parity check mechanism that continuously monitors data integrity. When a fault is detected, the feedback triggers the MMU to switch to an alternative static data copy. This feedback loop enables real-time fault response without system reset, maintaining continuous operation while identifying and correcting errors through the copy-switching mechanism.
Data Source
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AI summary
An example method for uninterrupted execution of control software in an aircraft control system includes creating a plurality of static data copies. A first parity bit is determined for each of the plurality of static data copies. A second parity bit is determined for a first static data copy. A parity fault is detected in the first static data copy if the first parity bit does not match the second parity bit. The system switches to read a second static data copy in response to detecting a parity fault in the first static data copy.