Parity Generation in Scan Paths for State Retention Integrity

Solution Overview

Problem

Data processing systems face challenges in maintaining state integrity of state retention circuits during low power modes due to vulnerability to soft errors, which can lead to unreliable operation upon exiting low power mode, and existing solutions like voltage margins and canary circuits increase power consumption or circuit area.

Innovation Solution

Incorporating parity information generation elements into the scan path of state retention circuits to generate parity information that inverts upon changes in state values, allowing for monitoring of state integrity and enabling timely error detection and recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage margin is increased to provide resistance to soft errors, then reliability is improved, but power consumption increases

Engineering Contradiction:

Improvestate integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces parity generation elements as an intermediary mechanism that monitors state retention circuits without requiring increased voltage margins. These elements generate parity information that can detect soft errors, providing reliability improvement through error detection rather than through voltage headroom, thus avoiding the power consumption penalty associated with higher voltage operation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If canary circuits are provided to support state retention integrity, then reliability is improved, but circuit area and power consumption increase

Engineering Contradiction:

Improvestate integrityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the functionality of state retention monitoring with the existing scan path infrastructure. By integrating parity generation elements into the scan path, the solution eliminates the need for separate canary circuits, thereby achieving reliability improvement without the additional circuit area overhead that would be required for dedicated monitoring structures.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The scan path is given multi-functionality by having it serve both its traditional testing/scan purpose and the new function of generating parity information for error detection. This universal usage of existing infrastructure avoids the need for additional dedicated monitoring circuits, thus preventing area increase while maintaining reliability improvement.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If canary circuits are provided to support state retention integrity, then reliability is improved, but power consumption increases

Engineering Contradiction:

Improvestate integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the functionality of state retention monitoring with the existing scan path infrastructure. By integrating parity generation elements into the scan path, the solution eliminates the need for separate canary circuits, thereby achieving reliability improvement without the additional circuit area overhead that would be required for dedicated monitoring structures.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The scan path is given multi-functionality by having it serve both its traditional testing/scan purpose and the new function of generating parity information for error detection. This universal usage of existing infrastructure avoids the need for additional dedicated monitoring circuits, thus preventing area increase while maintaining reliability improvement.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8639960B2Verifying state integrity in state retention circuits

Publication Date: 2014.01.28 ARM LTD

AI summary

A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits. The plurality of parity information generation elements are arranged to provide one or more parity path(s), such that an output parity value generated at an output of the parity path will invert if one of said respective state values changes, providing an external indication of the integrity of the state values held by the state retention circuits.