Information Processing Device Parity Checks for Soft Error Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional information processing devices face challenges in maintaining normal operation due to soft errors, particularly bit inversions caused by radiation and electromagnetic noise, which are exacerbated by semiconductor miniaturization and power saving, and existing error correction methods like ECC increase circuit size and memory requirements without effectively correcting memory content.
Innovation Solution
An information processing device that includes a control unit to write computer programs from an external memory to an internal memory, calculates parity values, and transfers instructions or data from the external memory when errors are detected, ensuring continued normal operation without the need for error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If semiconductor miniaturization and power saving are implemented, then device performance and energy efficiency are improved, but resistance to external influences such as radiation and electromagnetic noise decreases, resulting in increased soft error occurrence
Solution Approach 1:
The patent applies preliminary action by calculating and storing parity values for all instructions and data before they are executed from internal memory. This pre-computation of error detection information allows the system to quickly detect soft errors without adding complexity to the execution path, thereby maintaining power efficiency while improving reliability against radiation and electromagnetic noise.
Solution Approach 2:
The patent introduces parity values as an intermediary mechanism between the stored instructions/data and the execution unit. These parity values serve as a mediator that enables error detection without requiring direct complex verification of each bit, thus maintaining low power consumption while providing protection against soft errors caused by external influences.
2Reliability
If conventional error correction methods like ECC are used, then error correction capability is improved, but circuit size and memory requirements increase
Solution Approach 1:
The patent extracts only the essential error detection function by using simple parity bits rather than full ECC codes. This extraction approach removes the unnecessary complexity of comprehensive error correction while retaining the critical capability to detect soft errors, thereby reducing circuit size and memory requirements while maintaining improved reliability.
Solution Approach 2:
The patent employs simple parity bits as a lightweight, low-cost error detection mechanism compared to full ECC. These parity values are easily computable and require minimal storage, providing an economical solution that achieves error detection capability without the overhead of complex correction codes, thus reducing device complexity while maintaining reliability.
3Reliability
If parity values are calculated and stored for all instructions and data, then soft error detection capability is improved, but memory bandwidth and processing overhead increase
Solution Approach 1:
The patent applies preliminary action by computing and storing parity values during the initial loading of instructions and data from external memory to internal memory. This pre-computation approach ensures that error detection information is ready before execution, avoiding any overhead during the critical execution phase and maintaining high processing speed while achieving improved soft error detection capability.
4Speed
If internal memory is used for high-speed access to computer programs, then processing speed is improved, but vulnerability to bit inversion from soft errors increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing parity values alongside instructions and data in internal memory before execution. This allows the high-speed access capability of internal memory to be maintained while enabling rapid error detection through the pre-prepared parity information, thus resolving the contradiction between speed and reliability by preparing error detection mechanisms in advance without slowing down the execution path.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An information processing device (1) has a control unit (2) configured to write a program read from an external memory (3), in an internal memory (12) and execute the program. The information processing device includes a writing control unit (11), a reading control unit (13) and a transferring unit (14). The writing control unit is configured to calculate a parity value of an instruction or a set of data of the program, and write the instruction or the set of data and the parity value in the internal memory. The reading control unit is configured to determine, based on the parity value, presence or absence of an error in the instruction or the set of data. The transferring unit is configured to transfer, when the error has occurred, the instruction or the set of data read again from the external memory, to the control unit and the writing control unit.