Multi-Page Parity Storage Compression for Memory Write Performance
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Solution Overview
Problem
Memory sub-systems face inefficiencies in storing parity data due to frequent data integrity scans, which introduce latency and reduce performance, and the limited storage space for parity data can lead to parity data storage exhaustion, especially during extended periods without idle time.
Innovation Solution
Implementing a compression algorithm to convert multiple pages of uncompressed parity data into a single compressed parity page, allowing for reduced storage space consumption and minimizing the frequency of scan operations by initiating compression when parity block consumption exceeds a certain threshold, thereby extending the time before parity data release is necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent data integrity scans are performed to ensure parity data reliability, then data reliability is improved, but system performance deteriorates due to increased latency
Solution Approach 1:
The patent implements periodic scan operations at predetermined intervals instead of frequent continuous scanning. The controller performs scans at specific time intervals, reducing the overall scan frequency while still maintaining data integrity verification. This periodic approach allows the system to balance reliability checks with performance requirements by not continuously interrupting host operations.
Solution Approach 2:
The patent changes the timing parameter of scan operations from frequent to periodic at predetermined intervals. By adjusting the scan frequency parameter and implementing time-based triggering, the system optimizes the balance between verifying data integrity and maintaining system performance during host read/write operations.
2Reliability
If more parity data is stored to extend protection duration, then reliability is improved, but storage space is exhausted more quickly
Solution Approach 1:
The patent implements a mechanism where the controller releases parity data from storage when host pages are determined to be free from defects through scan operations. This discarding of redundant parity data recovers storage space, allowing the system to maintain adequate parity protection for active data while freeing space for new parity data generation. The system dynamically manages parity storage by releasing it when no longer needed.
Solution Approach 2:
The patent implements dynamic parity data management where the amount of stored parity data changes over time based on host operation patterns and scan results. The controller dynamically releases parity data when pages are verified as defect-free and generates new parity data as needed, creating a flexible system that adapts parity storage levels to current requirements rather than maintaining fixed high levels throughout.
3Area of stationary object
If parity data is released frequently to free storage space, then storage availability is improved, but data protection coverage is reduced
Solution Approach 1:
The patent implements a feedback mechanism where scan operation results directly control parity data release decisions. The controller continuously monitors host page health through scans and uses this feedback to determine when it is safe to release parity data. Only pages verified as defect-free through scan feedback trigger parity release, ensuring that protection coverage is maintained for at-risk data while freeing space for verified-safe data.
Solution Approach 2:
The patent replaces proactive frequent parity release with a reactive system triggered by scan results. Instead of mechanically releasing parity data on a fixed schedule or when space is needed, the system substitutes a condition-based approach where parity release occurs only when scan operations confirm host pages are defect-free, optimizing both storage availability and protection coverage.
Data Source
AI summary
A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device, to store host data in the page of the data unit. The processing device further generates a parity page for the host data stored in the page of the data unit and adds the parity page to parity data stored at a parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.


