Parsing Tree for Programmable Packet Processor Pipeline

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Solution Overview

Problem

The development of network packet processors is time-consuming and expensive due to the requirement of specialized knowledge from multiple fields of expertise, making rapid prototyping and iteration challenging.

Innovation Solution

A method is introduced that involves generating a parsing tree from a specification describing packet processor actions, which is then used to create a programmable compute pipeline with multiple stages, allowing for concurrent execution of elementary operations and easy modification of actions without regenerating the pipeline.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a hardware implementation of a network packet processor is created following traditional development methods, then the implementation can comply with protocol specifications, but the development process is time-consuming and expensive due to requiring specialized knowledge from multiple fields of expertise

Engineering Contradiction:

Improvecompliance with protocol specificationsVSAvoiddevelopment time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

A parsing tree is introduced as an intermediary data structure that bridges protocol specifications and hardware implementation. The parsing tree captures the hierarchical structure and concurrency requirements of packet processing protocols, enabling automated translation to hardware descriptions without requiring developers to simultaneously master multiple specialized fields

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The protocol specification is segmented into discrete actions that are organized into a parsing tree with multiple levels. Each level represents a stage in packet processing with bounded concurrent sets of elementary operations, allowing the complex protocol to be broken down into manageable, independently verifiable components

Inventive Principle:

Principle #1Segmentation

2Manufacturing precision

If traditional hardware development methods are used for packet processors, then implementation quality can be ensured, but rapid prototyping and iteration are challenging

Engineering Contradiction:

Improveimplementation qualityVSAvoidrapid prototyping capability

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The system enables dynamic iteration by allowing protocol specifications to be modified and reparsed into updated parsing trees, which then generate revised hardware descriptions. This dynamic process supports rapid prototyping while maintaining implementation quality through the structured parsing tree framework that ensures correctness at each iteration

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The parsing tree is constructed in advance to capture all concurrency bounds and operational dependencies before hardware generation. This preliminary structuring of the protocol specification enables subsequent rapid iterations without sacrificing implementation quality, as the foundational structure is already validated

Inventive Principle:

Principle #10Preliminary action

3Productivity

If the parsing tree specifies bounded concurrent sets of elementary operations at each level, then the programmable compute pipeline can be efficiently generated, but the device complexity increases due to multiple stages and elementary components

Engineering Contradiction:

Improvepipeline generation efficiencyVSAvoidpipeline structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The parsing tree specifies parameter bounds for concurrent sets of elementary operations at each level, which directly determines the number of elementary components needed in corresponding pipeline stages. By optimizing these bounds, the system achieves efficient pipeline generation while controlling device complexity through precise parameter specification rather than over-provisioning

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8358653B1Generating a pipeline of a packet processor from a parsing tree

Publication Date: 2013.01.22 XILINX INC

AI summary

A method or system for generating a packet processor inputs a first specification describing the packet processor, generates a parsing tree and generates a second specification describing a programmable compute pipeline. The parsing tree is generated from the actions of the first specification. The parsing tree has multiple levels and each level specifies one or more concurrent sets of elementary operations. The parsing tree also specifies for each level a respective bound on the elementary operations in the concurrent sets of the level. The programmable compute pipeline includes multiple stages for implementing the actions. Each stage corresponds to one of the levels of the parsing tree and includes one or more elementary components, with a number of the elementary components equaling or exceeding the respective bound for the level. The elementary components in the stage are programmable to concurrently perform combinations that include each concurrent set for the level.