Partial Air Spacer Structure for Low-Capacitance S/D Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming air gaps between semiconductor device features, such as S/D contacts and metal gate structures, are inadequate in preventing structural damage during subsequent processing steps, particularly due to inadvertent over-etching and chemical etchant penetration, which can damage surrounding dielectric components.
Innovation Solution
A method is introduced to form a partial air gap between S/D contacts and neighboring metal gate structures, where the upper portion of the air gap is filled with the interlayer dielectric material using controlled ion implantation, and a protective etch-stop layer is applied to seal the gap, thereby reducing parasitic capacitance while protecting the device structure from damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a complete air gap is formed between S/D contacts and metal gate structures, then parasitic capacitance is reduced, but structural damage occurs during subsequent processing steps due to over-etching and chemical etchant penetration
Solution Approach 1:
The patent applies local quality by creating a partial air gap structure where only the lower portion of the air gap is maintained, while the upper portion is filled with dielectric material. This localized differentiation allows the lower region to provide capacitance reduction while the upper region maintains structural protection, resolving the contradiction between energy loss reduction and reliability maintenance
Solution Approach 2:
The air gap is segmented into two distinct portions: a lower portion that remains as air gap for capacitance reduction and an upper portion that is filled with dielectric material for structural protection. This segmentation allows each portion to serve its specific function, simultaneously achieving both parasitic capacitance reduction and structural integrity protection
2Reliability
If ion implantation is used to fill the upper portion of the air gap, then structural protection is improved, but process complexity increases
Solution Approach 1:
The patent uses an intermediary etch-stop layer positioned between the lower and upper portions of the air gap. This intermediary layer facilitates the ion implantation process by providing a controlled interface, allowing the upper portion to be filled with dielectric material while maintaining precise control over the filling depth and protecting underlying structures, thus managing process complexity while achieving structural protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance while minimizing structural defects and damage to semiconductor components during subsequent processing steps, ensuring the integrity of the semiconductor device.
Implementation Method 1
bombarding the second interlayer dielectric layer with dopant particles, wherein the dopant particles cause the second interlayer dielectric layer to expand
Data Source
AI summary
A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.