Partial Buried-Insulator Nanosheet SRAM for Read Margin Gain
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Solution Overview
Problem
FinFET devices face short channel effects such as leakage currents, surface scattering, velocity saturation, impact ionization, threshold voltage variations, and hot carrier effects due to reduced gate length, which degrade their performance, and require additional read assist circuits in SRAM devices, occupying valuable space.
Innovation Solution
The implementation of a partial buried insulator (BI) nano-sheet device in SRAM bitcells, where a BI layer is formed beneath the source or drain region and nano-sheets separate the source and drain regions, enhancing gate controllability and eliminating the need for read assist circuits by increasing the β-ratio, thereby improving read performance without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate length of MOSFET is reduced to make devices smaller, then device size decreases, but transistor performance deteriorates due to reduced control over the channel region
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D FinFET structure with vertical fins, adding a vertical dimension to channel control. The gate electrode wraps around the fin structure, providing control from multiple directions (top, bottom, and sides), thereby maintaining effective channel control despite reduced gate length and enabling continued device scaling.
2Reliability
If FinFET is used to improve gate controllability, then channel control improves, but short channel effects increase due to reduced gate length
Solution Approach 1:
The patent introduces a buried insulator layer that segments the substrate into isolated regions beneath each FinFET structure. This segmentation electrically isolates adjacent fins and prevents harmful interactions between neighboring channels, thereby reducing short channel effects such as leakage currents and threshold voltage variations while maintaining strong gate controllability.
Solution Approach 2:
The buried insulator layer acts as an intermediary between the substrate and the FinFET structures. It provides electrical isolation and prevents direct interaction between the substrate and multiple fins, thereby mitigating short channel effects like substrate biasing and leakage currents that would otherwise degrade device performance.
3Reliability
If read assist circuits are added to SRAM devices to improve read performance, then read margins improve, but device area increases
Solution Approach 1:
The patent modifies the electrical parameters of the FinFET by introducing the buried insulator layer, which changes the current characteristics and transfer ratios of the transistor. This parameter change enables the FinFET to achieve sufficient read margins through its inherent structure, eliminating the need for additional read assist circuits and thereby reducing the overall SRAM cell area.
Data Source
AI summary
Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.