Partial Block Memory Operations in 3D NAND

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Solution Overview

Problem

As memory block size increases, especially in 3D memory devices, power consumption and parasitic current leakage rise due to the need to perform memory operations on larger pages, leading to inefficiencies in data access and storage.

Innovation Solution

Breaking the memory block into independent partial blocks allows for concurrent memory operations on selected subsets, reducing unnecessary power usage by isolating and controlling access lines and voltage sources for each partial block, thereby minimizing current consumption and leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the memory block size is increased to provide larger storage capacity, then the storage capacity is improved, but the power consumption and parasitic current leakage increase

Engineering Contradiction:
Improvestorage capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The memory block is divided into multiple independent partial blocks, each with its own set of access lines. This allows selective operation on smaller subsets of the total memory block, enabling large storage capacity while consuming power only for the actively accessed partial blocks rather than the entire block.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the page size is increased to improve data access efficiency, then the data access efficiency is improved, but the current consumption and parasitic current leakage increase

Engineering Contradiction:
Improvedata access efficiencyVSAvoidcurrent consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The memory block is segmented into partial blocks that can be independently accessed. This allows the system to maintain efficient data access by operating on appropriately sized partial blocks rather than forcing all operations to use the entire large page size, thereby reducing parasitic current leakage on unaccessed portions.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If the memory block is operated as a single unit to simplify control logic, then the control logic is simplified, but the power consumption increases due to unnecessary operations on unaccessed portions

Engineering Contradiction:
Improvecontrol logic complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by stationary object

Solution Approach 1:

The memory block is divided into independent partial blocks with dedicated access lines. While this increases structural complexity, it actually simplifies control logic by allowing precise selection of only the necessary partial blocks for operation, eliminating the need to power and control the entire block even when only a small portion is accessed.

Inventive Principle:
Principle #1Segmentation

4Quantity of substance

If additional power sources are added to support extensive current consumption in 3D memory devices, then the current consumption capacity is improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvecurrent consumption capacityVSAvoidmanufacturing difficulty
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

By segmenting the memory block into partial blocks with isolated access lines, the system reduces the total current consumption for any given operation. This eliminates the need for additional power sources, thereby avoiding increased manufacturing complexity while still supporting the current demands of 3D memory structures.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11626162B2Partial block memory operations
Publication Date: 2023.04.11 MICRON TECHNOLOGY INC
  • US11626162B2 patent drawing
  • US11626162B2 patent drawing
  • US11626162B2 patent drawing

AI summary

Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.