Partial Block Read Voltage Offsets for Word Line Misidentification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems experience increased error rates and reliability issues due to misidentification of word line types during read operations in partial block read operations, leading to violations of hard error limits.
Innovation Solution
Implementing read voltage offsets in memory systems that account for potential misidentifications of word line types by using improved offset tables to ensure that error limits are not exceeded, regardless of correct or incorrect identification of word line type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If different read voltages are applied to boundary word lines and inner word lines in partial block read operations, then read accuracy is improved, but the system becomes vulnerable to errors when word line types are misidentified
Solution Approach 1:
The patent applies parameter changes by using different read voltage offsets for boundary word lines and inner word lines. Boundary word lines use a first read voltage offset while inner word lines use a second read voltage offset, allowing the system to optimize read accuracy for each word line type. This resolves the technical contradiction by enabling precise reads for both types simultaneously.
Solution Approach 2:
The patent implements beforehand cushioning by designing the read voltage selection mechanism to handle misidentification scenarios. The system uses a table-driven approach with multiple voltage offset options, allowing it to compensate for potential word line type misidentification and maintain acceptable error rates even when identification fails.
2Productivity
If read voltage offsets are optimized for specific word line types, then read performance is improved, but device complexity increases due to the need for identification logic and voltage selection tables
Solution Approach 1:
The patent manages device complexity through parameter changes by using a table-driven voltage selection approach. Instead of complex real-time calculation logic, the system pre-defines voltage offset values in tables that can be directly indexed during read operations. This simplifies the implementation while maintaining optimized read performance for different word line types.
Solution Approach 2:
The patent applies copying by using a table-driven architecture where voltage selection parameters are pre-stored and copied during operation. The system copies the appropriate voltage offset values from lookup tables based on word line type identification, avoiding the need for complex real-time voltage generation logic and reducing overall device complexity.
Data Source
AI summary
Methods, systems, and devices for partial block read level design for a memory system are described. The memory system may store offsets for inner word lines and outer word lines of a partial block for use in read operations. For example, the memory system may read a boundary word line of the partial block using a read voltage configured with a boundary word line offset. Alternatively, the memory system may read an inner word line of the partial block using a read voltage configured with an inner word line offset. The offsets may avoid an error limit for a read operation being exceeded even in the event of a misidentification by the memory system of an inner word line as a boundary word line, of a boundary word line as an inner word line, or both.