3D Memory Array Staircase Routing With Partial Border Layout
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in increasing device density and efficiency, particularly in forming staircase structures for 3D memory arrays, where existing methods consume excessive space and are costly, leading to reduced performance and increased defects.
Innovation Solution
A method for forming a staircase structure in a 3D memory array by depositing and patterning a hard mask over word lines, forming a photoresist, and performing repeated trimming and etching processes, allowing the staircase structure to extend only partially along the borders of the memory array, thereby saving area and improving device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If staircase structures are formed along the entirety of the borders of the memory array, then connections can be made to various portions of the underlying substrate, but the area consumed is excessive and device density is reduced
Solution Approach 1:
The staircase structure is formed only along selected portions of the borders rather than the entire border perimeter. This partial action approach provides sufficient connection capability to the underlying substrate while consuming less area, thereby resolving the contradiction between adaptability and area consumption.
Solution Approach 2:
The border of the memory array is segmented into multiple sections, and staircase structures are formed only in specific segments rather than continuously along the entire border. This segmentation allows the structure to maintain necessary connection functionality while reducing the total area occupied.
2Ease of manufacture
If existing methods are used to form staircase structures, then the structure can be created, but the process is costly and consumes excessive space
Solution Approach 1:
The staircase structure is formed only where necessary along the borders, using partial action to reduce the overall footprint. This approach maintains manufacturability through standard deposition and patterning processes while significantly reducing the space consumed by the staircase structure.
3Reliability
If staircase structures extend along the entire border, then comprehensive connections are achieved, but device density and performance are reduced
Solution Approach 1:
The staircase structure is implemented in a partial manner along selected border portions, providing sufficient connection reliability for device operation while maximizing device density by minimizing the area occupied by the staircase structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device density by minimizing the footprint of the staircase structure, reducing defects, and enhancing performance by allowing for more efficient connections and better routing configurations, leading to improved memory array efficiency.
Implementation Method 1
depositing and patterning a hard mask over the word lines
Implementation Method 2
depositing and patterning a hard mask over the word lines
Implementation Method 3
forming a photoresist, and performing repeated trimming and etching processes
Implementation Method 4
performing repeated trimming and etching processes on the photoresist and the underlying word lines
Data Source
AI summary
Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.