Partial Cache Line Operations for Interconnect Traffic Reduction
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Solution Overview
Problem
Conventional symmetric multiprocessor systems experience inefficiencies due to memory accesses that require entire cache lines, leading to significant traffic on the system interconnect and undesirable cross-invalidation of cached data.
Innovation Solution
Implementing a method that allows for partial cache line operations, where a processing unit can initiate interconnect operations requesting a variable amount of data, with a snooper selecting and transmitting only the necessary data, reducing the amount of cached data subject to cross-invalidation and increasing local cache servicing of memory requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If entire cache lines are accessed in conventional SMP systems, then data coherency is maintained, but system interconnect traffic increases and cache invalidation overhead increases
Solution Approach 1:
The patent segments the cache line into multiple granules (e.g., 32-byte granules within a 128-byte cache line). Instead of accessing the entire cache line, the system can now access individual granules or subsets of granules. This segmentation allows selective invalidation of only the accessed granules rather than the entire cache line, reducing unnecessary memory traffic and invalidation overhead while maintaining data coherency for the specific accessed portions.
2Productivity
If partial cache line operations are implemented, then interconnect traffic is reduced, but system complexity increases
Solution Approach 1:
The patent implements partial action by allowing memory access requests to specify a subset of granules within a cache line rather than requiring access to the entire cache line. The interconnect operation includes a granule identifier field that enables selective addressing of specific granules. This partial action approach reduces the amount of data transferred over the interconnect and the scope of invalidation operations, improving system efficiency without requiring fundamental changes to the memory hierarchy architecture.
3Reliability
If full cache lines are transmitted, then data availability is ensured, but memory access latency increases
Solution Approach 1:
The patent extracts only the necessary granules from the cache line for transmission over the interconnect. Instead of transmitting the entire cache line when a portion is needed, the system extracts and transmits only the specific granules identified in the memory access request. This extraction mechanism reduces the volume of data transmitted, thereby reducing memory access latency while ensuring that the required data is available to the requesting processor core.
Data Source
AI summary
According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.