Partial Cache Line Sourcing in Multi-Level Cache Hierarchy
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Solution Overview
Problem
Conventional cache hierarchies in multiprocessor systems incur inefficiency by retrieving and caching entire cache lines when only a small portion needs to be updated, leading to increased access latency and resource wastage in workloads without spatial or temporal locality.
Innovation Solution
A multi-level cache hierarchy where the lower level cache sources partial cache lines to the upper level cache to service memory access requests without caching them, allowing partial cache lines to be prefetched and stored only in the lower level cache, thereby reducing unnecessary caching in upper level caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the conventional cache hierarchy retrieves a full cache line from system memory, then the memory access request can be serviced, but the access latency increases and cache resources are wasted when only a partial cache line is needed
Solution Approach 1:
The patent segments the cache line transfer operation into partial cache line transfers. Instead of transferring entire cache lines (typically 64 bytes), the system transfers only the specific bytes or words needed by the processor. This is achieved by modifying the cache control logic to support granular transfer sizes, allowing the cache to service memory requests with partial line transfers, thereby reducing memory bandwidth consumption and improving access efficiency for workloads without spatial locality.
Solution Approach 2:
The patent applies partial action by transferring only the necessary portion of the cache line rather than the complete cache line. When a memory request needs only part of a cache line, the system performs a partial transfer of that specific portion, avoiding the overhead of transferring and caching unnecessary data. This partial action principle directly addresses the inefficiency of full cache line transfers in workloads where entire lines are not reused.
2Speed
If the conventional cache hierarchy caches entire cache lines in upper level caches, then data can be quickly accessed, but cache resources are wasted on data unlikely to be accessed again
Solution Approach 1:
The patent segments the cache storage function to distinguish between partial cache line storage and full cache line storage. The upper level caches continue to cache full cache lines for workloads with spatial locality, while the lower level caches handle partial cache line transfers for workloads without spatial locality. This segmentation allows the cache hierarchy to optimize for different workload characteristics simultaneously, maintaining high access speed for appropriate workloads while avoiding resource wastage.
Solution Approach 2:
The patent applies local quality by assigning different caching behaviors to different levels of the cache hierarchy based on local characteristics. The lower level caches are configured to accept and store partial cache lines with reduced caching semantics, while upper level caches maintain full caching capabilities. This local differentiation allows each cache level to operate optimally for its intended workload type, preventing resource wastage in the upper caches while maintaining fast access where applicable.
3Adaptability or versatility
If the cache hierarchy services updates to scattered memory locations, then all memory updates can be handled, but entire cache lines must be retrieved and cached even when only small portions are updated
Solution Approach 1:
The patent segments the memory update operation to allow updates at the byte or word level rather than requiring full cache line transfers. When updating scattered memory locations, the system identifies only the specific bytes or words that need modification and transfers only those portions through the cache hierarchy. This segmentation capability maintains full adaptability for handling various update patterns while dramatically reducing the quantity of cache data that must be manipulated.
Solution Approach 2:
The patent extracts the essential update operation from the full cache line transfer context. Instead of retrieving and caching entire cache lines to perform updates, the system extracts and transfers only the specific data elements that require modification. This extraction approach allows the cache hierarchy to service updates to scattered memory locations efficiently, handling the update capability requirement while minimizing cache data volume and avoiding the overhead of transferring unnecessary data.
Data Source
AI summary
A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.