Partial Cache Line Sparing for DRAM Error Correction
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Solution Overview
Problem
Current sparing techniques in DRAM systems often require replacing large sections of memory to address single bit failures, which is inefficient and wasteful, as around 50% of hard errors in DRAM are single bit fails.
Innovation Solution
Implementing partial cache line sparing by focusing on replacing only the specific nibble or subset of bits within a cache line that experiences the hard bit error, using a sparing directory to store substitute data within the memory controller, thus limiting the affected area to just the failing bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row sparing or rank sparing is used to replace defective bits, then reliability is improved, but loss of substance increases due to replacement of large memory sections
Solution Approach 1:
The patent segments the cache line into multiple nibbles (4-bit units) and implements sparing at the nibble level rather than replacing entire rows or ranks. When a bit error is detected, only the specific nibble containing the error is marked for sparing, allowing the rest of the memory to remain functional. This segmentation approach directly resolves the contradiction by maintaining reliability through error correction while minimizing memory capacity loss.
Solution Approach 2:
The patent applies local quality by treating different portions of the cache line differently based on their error status. Good nibbles remain accessible while defective nibbles are marked for sparing. The sparing directory maintains metadata at the nibble level, allowing selective access to good portions of cache lines while isolating only the defective portions. This local differentiation resolves the contradiction by preserving overall system reliability while minimizing the impact on usable memory capacity.
2Reliability
If row sparing or rank sparing is used to address single bit failures, then reliability is improved, but productivity decreases due to inefficient memory usage
Solution Approach 1:
By segmenting the error handling to the nibble level rather than row or rank level, the patent enables fine-grained memory management. When a single bit fails, only the minimal necessary portion (one nibble) is marked for sparing, allowing the majority of the memory to continue operating at full productivity. This segmentation approach directly addresses the contradiction by maintaining reliability while maximizing memory utilization efficiency.
Solution Approach 2:
The patent applies partial action by implementing sparing only for the specific nibble containing the error rather than sparing entire rows or ranks. The sparing directory maintains partial metadata information at the nibble level, enabling selective correction without affecting the rest of the memory. This partial approach resolves the contradiction by ensuring reliability for defective bits while maintaining high productivity for error-free memory regions.
Data Source
AI summary
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.