Partial Cache Way Locking for Processor Efficiency

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Solution Overview

Problem

Conventional cache systems waste space by locking entire cache ways, which reduces the efficiency of cache usage for high-priority and frequently used code, as they do not allow for precise locking of smaller portions of cache space, leading to inefficiencies in processor performance.

Innovation Solution

A cache system that allows for the division of cache ways into smaller portions, enabling precise locking of only the necessary cache space for high-priority or frequently used code, using a partial cache way signal and locked portions signal to manage which cache way portions are locked or unlocked, thereby optimizing cache space usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If entire cache ways are locked to ensure high-priority code availability, then reliability of code access is improved, but cache space utilization deteriorates

Engineering Contradiction:
Improvecode access availabilityVSAvoidcache space utilization
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The cache way is divided into multiple cache way portions, allowing selective locking of individual portions rather than locking the entire cache way. This segmentation enables precise control over which parts of the cache are reserved for high-priority code while leaving other portions available for general use, thus improving space utilization while maintaining reliability for critical code access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the cache way are assigned different functions: some portions are locked for high-priority code to ensure availability, while other portions remain unlocked for general cache operations. This local differentiation optimizes both reliability for critical code and space utilization for the overall cache system.

Inventive Principle:
Principle #3Local quality

2Productivity

If more cache ways are locked to improve processor speed, then productivity is improved, but cache space waste increases

Engineering Contradiction:
Improveprocessor speedVSAvoidcache space waste
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

By segmenting cache ways into multiple portions and enabling selective locking of only the necessary portions for high-priority code, the system achieves the productivity benefits of cached code execution without wasting cache space on unnecessarily locked portions. This allows the processor to access critical code quickly while maximizing the use of available cache space.

Inventive Principle:
Principle #1Segmentation

3Loss of substance

If cache ways are divided into smaller portions for precise locking, then cache space efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvecache space efficiencyVSAvoidcache control structure
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The cache way is divided into multiple cache way portions with associated control signals (partial cache way signal and locked portions signal). While this segmentation improves space efficiency, the control mechanism is designed to manage the increased complexity through structured signaling that indicates which portions are locked versus available, balancing efficiency gains with acceptable control complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7676632B2Partial cache way locking
Publication Date: 2010.03.09 VIA TECH INC
  • US7676632B2 patent drawing
  • US7676632B2 patent drawing
  • US7676632B2 patent drawing

AI summary

Systems and methods are disclosed for locking code in cache. A processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main memory. Also, the cache is divided into a number of cache ways, where each cache way is further divided into a number of cache way portions. The cache controller is configured to utilize a first signal and a second signal. The first signal designates one of the cache ways as a partial cache way and the second signal defines which ones of the cache way portions of the partial cache way are to be locked.