Partial Chip Segmentation for Memory Test Time Reduction
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Solution Overview
Problem
Memory devices face challenges when dealing with defective memory cells, as they often require entire blocks to be disabled, leading to reduced operational efficiency and increased test times during parallel bit test (PBT) operations.
Innovation Solution
A partial chip design that includes a memory cell array with a pass region and a fail region, where a signal control circuit generates second data corresponding to first data from the fail region, setting it to logic high or low, and bypasses data from the pass region to a data comparison circuit during PBT, allowing for selective operation and reduced test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If entire blocks containing defective cells are disabled, then reliability is maintained, but productivity decreases due to reduced operational efficiency
Solution Approach 1:
The memory device is segmented into multiple blocks, and further divided into pass regions and fail regions based on cell functionality. This allows selective operation of only the healthy pass regions while disabling only the necessary fail regions, thereby maintaining reliability through defect isolation while improving productivity by utilizing available functional blocks
Solution Approach 2:
Different regions of the memory device are assigned different operational statuses based on their quality. Pass regions with functional cells operate normally, while fail regions with defective cells are disabled. This local differentiation allows the memory device to maintain high reliability in critical areas while maximizing productivity in functional areas
2Reliability
If entire blocks are disabled during PBT operation, then defective cells are isolated, but test time increases
Solution Approach 1:
The memory device is divided into pass and fail regions, allowing the PBT operation to focus testing efforts only on the fail regions rather than scanning entire blocks. This segmented approach maintains reliable defect isolation while significantly reducing test time by excluding already-verified pass regions from extensive testing
Solution Approach 2:
The memory device performs preliminary identification and classification of regions into pass and fail categories before comprehensive PBT operation. This preliminary action allows the system to pre-isolate defective areas and plan testing sequences that minimize overall test time while ensuring complete defect detection
3Measurement precision
If signal control circuit generates data for fail region, then test coverage is improved, but device complexity increases
Solution Approach 1:
The signal control circuit is designed with multi-functionality, serving both as a control element for region selection and as a data generation source for fail regions during PBT. By integrating these functions into a single circuit component, the patent improves test coverage without proportionally increasing device complexity
Solution Approach 2:
The signal control circuit generates test data for fail regions by copying or deriving from the actual data stored in those regions. This copying mechanism enables comprehensive test coverage of fail regions without requiring separate test data storage, thereby improving measurement precision while keeping the circuit structure relatively simple
Data Source
AI summary
A partial chip and a system including the partial chip are provided. The partial chip includes a memory cell array and a signal control circuit. The memory cell array includes a pass region and a fail region. The signal control circuit is configured to generate second data corresponding to first data to be output from the fail region.