Partial Circuit Design Testing with Traffic Generator
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Solution Overview
Problem
Current testing methods for circuit designs require all circuit modules to be fully realized, making it impractical to evaluate interactions and performance in early stages of system design, leading to additional development costs and time due to late redesigns.
Innovation Solution
A method for testing partial circuit designs by identifying unconnected ports and adding a traffic generator circuit to simulate master-to-slave communication patterns, allowing for the evaluation of circuit operation and performance before the design is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all circuit modules are fully realized before testing, then testing accuracy is improved, but development time and cost increase
Solution Approach 1:
The patent applies preliminary action by performing testing on partial circuit designs before all modules are fully realized. The system identifies unconnected ports in the partial design and prepares test configurations in advance, allowing early validation of completed modules without waiting for the entire design to be finished. This reduces development time while maintaining testing accuracy for the portions that are ready.
Solution Approach 2:
The patent segments the testing process into manageable parts by testing individual circuit modules or subsystems independently before integration. The system divides the overall design into testable units, allowing each segment to be validated separately. This segmentation enables early testing of completed portions without requiring the complete system to be ready, thus reducing overall development time.
2Reliability
If all circuit modules are fully realized before testing, then circuit interaction evaluation is improved, but development cost increases
Solution Approach 1:
The patent performs preliminary evaluation of circuit interactions by testing partial designs before full implementation. The system identifies potential interaction issues early in the development process by testing completed modules with simulated or placeholder components for unfinished sections. This early detection prevents costly redesigns later while maintaining reasonable evaluation accuracy.
Solution Approach 2:
The patent applies partial action by testing only the portions of the circuit design that are complete and ready for validation. Rather than requiring 100% completion for any testing, the system performs partial testing on available modules. This approach provides sufficient interaction evaluation for completed sections without incurring the full cost of completing and testing the entire design.
3Measurement precision
If testing is delayed until design completion, then comprehensive system validation is improved, but redesign time increases
Solution Approach 1:
The patent segments validation into multiple phases: partial system validation on completed modules, followed by full system validation upon completion. This multi-phase approach allows early detection of design errors in completed portions, enabling targeted redesigns rather than comprehensive system redesigns. The segmentation of validation reduces overall redesign time by catching issues early when they affect smaller portions of the system.
Solution Approach 2:
The patent performs preliminary validation of circuit modules before full system integration. By validating individual modules and subsystems early, the system identifies and corrects design errors before they propagate to the complete system. This preliminary validation reduces the scope and time required for any necessary redesigns, as errors are caught when they affect smaller, more manageable portions of the design.
Data Source
AI summary
Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.