Memory Controller ECC Rate Switching via Partial Codeword Decoding
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Solution Overview
Problem
Existing memory systems face challenges in varying error correction code rates without significant changes to the system design, as traditional methods require altering the size of memory components, which is impractical.
Innovation Solution
A memory controller that employs an error correction encoder and decoder capable of switching between different code rates by using separate parity check matrices and log likelihood ratio values for partial and entire codewords, allowing for error correction decoding at various code rates without changing the message length or memory component sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used, then data reliability is improved, but the system design becomes complex and inflexible when code rate variation is needed
Solution Approach 1:
The error correction decoder is designed to perform multiple decoding operations (first error correction decoding and second error correction decoding) using different code rates. The same decoder hardware can switch between different parity check matrices and code rates, making the system versatile without requiring separate decoding circuits for each code rate, thus reducing overall system complexity while maintaining data reliability.
Solution Approach 2:
The system dynamically switches between different code rates based on operational requirements. The error correction decoder can select between first error correction decoding at a first code rate and second error correction decoding at a second code rate, allowing the system to adapt its error correction capability dynamically without physical reconfiguration, thereby reducing design complexity while ensuring reliable operation under varying conditions.
2Reliability
If code rate is varied to improve error correction performance, then data reliability is improved, but memory component sizes must be altered
Solution Approach 1:
The system changes operational parameters (code rate, parity check matrix selection, LLR value usage) rather than physical dimensions. By varying the code rate between first and second error correction decoding operations and switching between different parity check matrices, the system achieves different error correction capabilities without altering the physical size of memory components, thus improving reliability while maintaining fixed hardware architecture.
3Adaptability or versatility
If separate parity check matrices are used for different code rates, then code rate flexibility is improved, but processing complexity increases
Solution Approach 1:
Multiple parity check matrices are pre-configured and stored in the error correction decoder before operation. The first parity check matrix and second parity check matrix are both prepared in advance, allowing the decoder to quickly switch between them based on the required code rate without performing complex real-time calculations, thus achieving code rate flexibility while minimizing processing complexity during actual operation.
Data Source
AI summary
A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.