Partial CRC Packet Forwarding for Lower Latency Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic systems, increasing clock frequency to enhance bandwidth and decrease latency leads to higher error rates due to noise and other factors, and the use of cyclical redundancy checks (CRC) increases latency and bandwidth consumption, especially for small messages, impacting performance in coherent systems.
Innovation Solution
Implementing a node with a packet scheduler and interface circuit that schedules packets for transmission, generates error detection data, and inserts partial error detection data within the packet, allowing for early forwarding of data and reducing CRC overhead by packing multiple packets with a single CRC or inserting partial CRCs within packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to increase bandwidth and decrease latency, then the bandwidth and speed improve, but the error rate increases due to noise and shorter clock cycle margins
Solution Approach 1:
The patent applies preliminary action by performing error detection on portions of data packets before the entire packet is received. The receiver generates and compares CRC codes for received data portions immediately, allowing early error detection without waiting for the complete packet including the trailing CRC field. This enables proactive identification of erroneous data while maintaining high clock frequencies.
2Reliability
If a CRC code is appended to the end of each data transfer for error detection, then the reliability improves through error detection capability, but the latency increases because the receiver must store the entire data until the CRC is received and validated
Solution Approach 1:
The patent applies segmentation by dividing the error detection process into segments corresponding to portions of the data packet. Instead of computing one large CRC for the entire packet, the receiver computes CRCs for individual data portions (e.g., cache lines or smaller units) as they are received. This segmentation allows incremental validation and early forwarding of correct data portions without waiting for the complete packet.
Solution Approach 2:
The receiver performs preliminary error detection by computing and validating CRC codes for data portions before the entire packet is received. This preliminary action enables the receiver to identify and forward correct data portions immediately upon validation, rather than waiting for the trailing CRC field to arrive and then validating the entire packet at once.
3Reliability
If a CRC code is added to each data transfer for error detection, then the reliability improves, but the bandwidth consumption increases significantly for small messages because the CRC size can be 50% or more of the message size
Solution Approach 1:
The patent applies segmentation by dividing data packets into smaller portions and computing separate CRC codes for each portion. This segmentation reduces the overhead ratio because each small data portion carries its own compact CRC rather than requiring the entire message to be padded to accommodate a full-size CRC. The total CRC overhead is distributed and optimized for the actual data size.
Solution Approach 2:
The patent applies parameter changes by adjusting the CRC computation parameters (such as polynomial degree and code length) based on the size of the data portion being transmitted. For smaller data portions, shorter and more efficient CRC codes are used, optimizing the trade-off between error detection capability and bandwidth consumption. This adaptive parameter adjustment reduces overhead for small messages while maintaining adequate error detection for larger transfers.
Data Source
AI summary
In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.