Partial Decoding Circuit for Video Encoder Inverse Second Transform
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Solution Overview
Problem
Conventional video coding standards face challenges in implementing efficient and cost-effective inverse second transform and second transform processes in video encoders and decoders, requiring innovative designs for high performance and low cost.
Innovation Solution
The design of partial decoding and encoding circuits with transpose buffers and directional transform circuits that process partial residual transform data in parallel, utilizing shared processing kernels for inverse and residual transforms, respectively, to achieve efficient and cost-effective transformations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-stage inverse transform and second transform are implemented in video encoder/decoder, then transform performance is improved, but device complexity increases
Solution Approach 1:
The inverse second transform is divided into two separate directional transform circuits (first-direction and second-direction) that process data in different orientations. This segmentation allows the complex multi-stage transform to be broken down into manageable, independent processing stages that can be implemented with simpler individual circuits while maintaining overall transform performance.
Solution Approach 2:
The transpose buffer serves multiple functions: it stores intermediate transform results, enables data reordering for different processing directions, and facilitates parallel processing between encoding and decoding operations. This multi-functionality reduces the need for separate dedicated circuits for each operation, thereby reducing overall device complexity while maintaining transform performance.
2Productivity
If parallel processing of inverse and residual transforms is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The first-direction inverse residual transform circuit and the second-direction residual transform circuit are merged into a unified processing architecture that shares common resources including the transpose buffer and processing kernels. This merging enables parallel processing of inverse and residual transforms simultaneously, improving productivity while avoiding the need for completely separate circuit implementations that would increase complexity.
Solution Approach 2:
The transpose buffer acts as an intermediary structure that enables parallel processing by temporarily storing intermediate transform results and providing ordered data access for both inverse and residual transform operations. This intermediary mechanism allows multiple transform operations to proceed concurrently without requiring complex synchronization logic, thereby improving productivity with minimal increase in device complexity.
3Device complexity
If shared processing kernels are used for inverse and residual transforms, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The shared processing kernels are configured with direction-specific processing parameters and coefficients that are applied locally to data based on the processing direction (first-direction or second-direction). This local quality approach allows the same physical circuit to perform different transform operations with direction-appropriate precision requirements, reducing overall device complexity while maintaining the necessary manufacturing precision for each specific transform type through localized parameter configuration.
Data Source
AI summary
A partial decoding circuit with inverse second transform has a transpose buffer, a first-direction inverse residual transform circuit, and a second-direction inverse residual transform circuit. The transpose buffer stores an intermediate inverse residual transform result. The first-direction inverse residual transform circuit processes an inverse quantization output to generate the intermediate inverse residual transform result to the transpose buffer. The second-direction inverse residual transform circuit accesses the transpose buffer to retrieve the intermediate inverse residual transform result, and processes the intermediate inverse residual transform result to generate a final inverse residual transform result, where the final inverse residual transform result of the inverse second transform is further processed by an inverse transform circuit. The first-direction inverse residual transform circuit and the second-direction inverse residual transform circuit process partial residual transform data of different process units in a parallel processing manner.


