Partial Emulation Processor for ISA Code Translation

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Solution Overview

Problem

Conventional processor implementations using co-designed virtual machines suffer from performance losses due to full emulation, where all code must be interpreted or translated before execution, leading to inefficiencies, especially for frequently executed regions.

Innovation Solution

Implementing partial emulation in processors, allowing direct execution of source ISA instructions and translation of frequently executed regions into optimized target ISA code stored in a translation cache, with hardware-assisted control transfer mechanisms that avoid modifying conventional memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If full emulation is used to translate all source ISA code to target ISA code, then code optimization and hardware feature utilization are improved, but startup latency and execution time increase significantly

Engineering Contradiction:

Improvepower efficiencyVSAvoidstartup latency

Core Design Contradiction:

PowerVSLoss of time

Solution Approach 1:

The patent applies partial emulation by selectively translating only frequently executed code regions (hotspots) to target ISA code while leaving other regions in source ISA format. This resolves the contradiction by achieving power efficiency benefits through translation of critical paths without incurring the full time penalty of translating entire codebases, thus balancing optimization gains against startup latency.

Inventive Principle:

Principle #16Partial or excessive action

2Productivity

If all code is translated to target ISA code before execution, then performance is improved for optimized code paths, but memory bandwidth consumption and translation overhead increase

Engineering Contradiction:

Improveexecution performanceVSAvoidtranslation overhead

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent segments the codebase into frequently executed regions and less frequently executed regions, applying translation only to the former. This segmentation allows the system to achieve performance improvements for critical paths while minimizing the energy overhead of translation, as only essential code portions undergo the translation process.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If interpretation is used for all code regions, then implementation simplicity is maintained, but execution speed and performance degrade

Engineering Contradiction:

Improveemulation complexityVSAvoidexecution speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent applies partial translation to frequently executed code regions while using interpretation for other regions. This approach maintains implementation simplicity for non-critical paths through interpretation while achieving execution speed improvements for hotspots through translation, thus resolving the contradiction between complexity and performance.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8775153B2Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment

Publication Date: 2014.07.08 INTEL CORP

AI summary

In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.