Partial Erase Strategy for Non-Volatile Memory Latency
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Solution Overview
Problem
Conventional memory systems experience performance degradation and increased latency when programming large volumes of data due to the time required for erasing multiple memory blocks, which delays the program operation and affects operational reliability.
Innovation Solution
A memory system that performs a first erase operation on memory blocks before they are allocated for new data, splitting the erase process into two phases: an initial phase that completes 80-90% of the erase operation in the background and a secondary phase that verifies and completes the erase operation when the block is allocated, reducing the time needed for the entire erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete erase operation is performed on memory blocks before allocation, then data reliability is improved, but programming time and latency increase significantly
Solution Approach 1:
The patent applies preliminary action by performing partial erase operations (first erase operation) on memory blocks in advance before they are allocated for new data. This preliminary partial erase reduces the remaining erase workload when the block is actually needed, thereby reducing programming latency while maintaining data reliability through the subsequent verification and completion steps.
Solution Approach 2:
The patent segments the complete erase operation into two distinct phases: a first erase operation performed in advance (completing 80-90% of the erase), and a second erase operation performed when the block is allocated (completing the remaining 10-20%). This segmentation allows the system to balance between erasing completeness for reliability and time spent on erasing for performance.
2Reliability
If multiple memory blocks are erased sequentially, then complete data erasure is achieved, but overall system productivity decreases due to cumulative erase time
Solution Approach 1:
The system performs preliminary partial erase operations on memory blocks that will be reused, so that when new data needs to be programmed, the blocks are already partially erased. This eliminates the need to wait for complete sequential erasure of multiple blocks, thereby improving productivity while maintaining erasure completeness through the second erase phase.
Solution Approach 2:
The patent introduces dynamic adaptability by determining whether to perform the second erase operation based on verification results. If the first erase operation successfully erased sufficient data (80-90%), the system can skip the second erase operation, dynamically adjusting the process based on actual conditions to maximize productivity while ensuring reliability when needed.
3Measurement precision
If erase verification is performed for every memory block, then erase accuracy is improved, but operational complexity and time consumption increase
Solution Approach 1:
The patent applies partial action by performing verification only when necessary (i.e., when allocating memory blocks for new data). Rather than continuously verifying every block, the system verifies selectively based on operational context, reducing complexity while maintaining accuracy where it matters most for data programming reliability.
Data Source
AI summary
A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.